Printable Version



Overview TOP


Overview
Generated on Thu Jan 22 11:45:02 2009
EDK Version 10.1.03
FPGA Family spartan3a
Device xc3s700afg484-4
# IP Instantiated 16
# Processors 1
# Busses 3



Block Diagram TOP


BlockDiagram



External Ports TOP


EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
fpga_0_RS232_DCE_RX_pin I 1 fpga_0_RS232_DCE_RX
fpga_0_RS232_DCE_TX_pin O 1 fpga_0_RS232_DCE_TX
fpga_0_RS232_DTE_RX_pin I 1 fpga_0_RS232_DTE_RX
fpga_0_RS232_DTE_TX_pin O 1 fpga_0_RS232_DTE_TX
fpga_0_DDR2_SDRAM_DDR2_ODT_pin O 1 fpga_0_DDR2_SDRAM_DDR2_ODT
fpga_0_DDR2_SDRAM_DDR2_Addr_pin O 0:0 fpga_0_DDR2_SDRAM_DDR2_Addr
fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin O 0:0 fpga_0_DDR2_SDRAM_DDR2_BankAddr
fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CAS_n
fpga_0_DDR2_SDRAM_DDR2_CE_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CE
fpga_0_DDR2_SDRAM_DDR2_CS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CS_n
fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_RAS_n
fpga_0_DDR2_SDRAM_DDR2_WE_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_WE_n
fpga_0_DDR2_SDRAM_DDR2_Clk_pin O 1 fpga_0_DDR2_SDRAM_DDR2_Clk  CLK 
fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_Clk_n  CLK 
fpga_0_DDR2_SDRAM_DDR2_DM_pin O 0:0 fpga_0_DDR2_SDRAM_DDR2_DM
fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin I 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I
fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin O 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O
fpga_0_DDR2_SDRAM_DDR2_DQS IO 0:0 fpga_0_DDR2_SDRAM_DDR2_DQS
fpga_0_DDR2_SDRAM_DDR2_DQS_n IO 0:0 fpga_0_DDR2_SDRAM_DDR2_DQS_n
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
fpga_0_DDR2_SDRAM_DDR2_DQ IO 0:0 fpga_0_DDR2_SDRAM_DDR2_DQ
sys_clk_pin I 1 dcm_clk_s  CLK 
sys_rst_pin I 1 sys_rst_s  RESET 
vga_16bit_ML403_plbv46_0_v_sync_pin O 1 vga_16bit_ML403_plbv46_0_v_sync
vga_16bit_ML403_plbv46_0_h_sync_pin O 1 vga_16bit_ML403_plbv46_0_h_sync
vga_16bit_ML403_plbv46_0_blue_pin O 0:0 vga_16bit_ML403_plbv46_0_blue
vga_16bit_ML403_plbv46_0_green_pin O 0:0 vga_16bit_ML403_plbv46_0_green
vga_16bit_ML403_plbv46_0_red_pin O 0:0 vga_16bit_ML403_plbv46_0_red
vga_16bit_ML403_plbv46_0_pixel_clk_pin O 1 vga_16bit_ML403_plbv46_0_pixel_clk
vga_16bit_ML403_plbv46_0_blank_z_pin O 1 vga_16bit_ML403_plbv46_0_blank_z
sys_clk50_pin I 1 sys_clk50  CLK 
xps_iic_0_Sda_pin IO 1 xps_iic_0_Sda
xps_iic_0_Scl_pin IO 1 xps_iic_0_Scl
video_in_rgb_0_VDEC1_PWRDN_Z_pin O 1 video_in_rgb_0_VDEC1_PWRDN_Z
video_in_rgb_0_VDEC1_OE_Z_pin O 1 video_in_rgb_0_VDEC1_OE_Z
video_in_rgb_0_RESET_VDEC1_Z_pin O 1 video_in_rgb_0_RESET_VDEC1_Z
video_in_rgb_0_LLC_CLOCK_pin I 1 video_in_rgb_0_LLC_CLOCK  CLK 
video_in_rgb_0_YCrCb_in_pin I 0:0 video_in_rgb_0_YCrCb_in
xps_sdi_master_module_0_led_debug_pin O 0:0 xps_sdi_master_module_0_led_debug



Processors TOP

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor


microblaze_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 MB_RESET I 1 mb_reset
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
MASTER DLMB LMB dlmb dlmb_cntlr
MASTER ILMB LMB ilmb ilmb_cntlr
MASTER DPLB PLBV46 mb_plb xps_iic_0
MASTER IPLB PLBV46 mb_plb xps_iic_0
TARGET DEBUG XIL microblaze_0_dbg debug_module


General
IP Core microblaze
Version 7.10.d
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3a
C_INSTANCE
Instance Name
microblaze_0
C_DCACHE_BASEADDR
D-Cache Base Address
0x00000000
C_DCACHE_HIGHADDR
D-Cache High Address
0x3FFFFFFF
C_ICACHE_BASEADDR
I-Cache Base Address
0x00000000
C_ICACHE_HIGHADDR
I-Cache High Address
0x3FFFFFFF
C_ADDR_TAG_BITS
Number of I-Cache Address Tag Bits
0
C_ALLOW_DCACHE_WR
Enable D-Cache Writes
1
C_ALLOW_ICACHE_WR
Enable I-Cache Writes
1
C_AREA_OPTIMIZED
Select implementation to optimize area (with lower instruction throughput)
1
C_CACHE_BYTE_SIZE
Size of the I-Cache in Bytes
8192
C_DATA_SIZE
C_DATA_SIZE
32
C_DCACHE_ADDR_TAG
Number of D-Cache Address Tag Bits
0
C_DCACHE_ALWAYS_USED
Use Cache Links for All D-Cache Memory Accesses
0
C_DCACHE_BYTE_SIZE
Size of D-Cache in Bytes
8192
C_DCACHE_LINE_LEN
Data Cache Line Length
4
C_DCACHE_USE_FSL
Enable Xilinx Cache Links for D-Cache
1
C_DEBUG_ENABLED
Enable MicroBlaze Debug Module Interface
1
C_DIV_ZERO_EXCEPTION
Enable Integer Divide-by-zero Exception
0
C_DOPB_BUS_EXCEPTION
Enable Data-side OPB Exception
0
C_DPLB_BURST_EN
C_DPLB_BURST_EN
0
C_DPLB_BUS_EXCEPTION
Enable Data-side PLB Exception
0
C_DPLB_DWIDTH
C_DPLB_DWIDTH
64
C_DPLB_NATIVE_DWIDTH
C_DPLB_NATIVE_DWIDTH
32
C_DPLB_P2P
C_DPLB_P2P
0
C_DYNAMIC_BUS_SIZING
C_DYNAMIC_BUS_SIZING
1
C_D_LMB
C_D_LMB
1
C_D_OPB
C_D_OPB
0
C_D_PLB
C_D_PLB
1
C_EDGE_IS_POSITIVE
Sense Interrupt on Rising vs. Falling Edge
1
C_FPU_EXCEPTION
Enable Floating Point Unit Exceptions
0
C_FSL_DATA_SIZE
FSL Link Data Width
32
C_FSL_EXCEPTION
Enable FSL Exception
0
C_FSL_LINKS
Number of FSL Links
0
C_ICACHE_ALWAYS_USED
Use Cache Links for All I-Cache Memory Accesses
0
C_ICACHE_LINE_LEN
Instruction Cache Line Length
4
C_ICACHE_USE_FSL
Enable Xilinx Cache Links for I-Cache
1
C_ILL_OPCODE_EXCEPTION
Enable Illegal Instruction Exception
0
 
Name Value
C_INTERCONNECT
Select Processor Local Bus (PLB) interface
1
C_INTERRUPT_IS_EDGE
Sense Interrupt on Edge vs. Level
0
C_IOPB_BUS_EXCEPTION
Enable Instruction-side OPB Exception
0
C_IPLB_BURST_EN
C_IPLB_BURST_EN
0
C_IPLB_BUS_EXCEPTION
Enable Instruction-side PLB Exception
0
C_IPLB_DWIDTH
C_IPLB_DWIDTH
64
C_IPLB_NATIVE_DWIDTH
C_IPLB_NATIVE_DWIDTH
32
C_IPLB_P2P
C_IPLB_P2P
0
C_I_LMB
C_I_LMB
1
C_I_OPB
C_I_OPB
0
C_I_PLB
C_I_PLB
1
C_MMU_DTLB_SIZE
Data Shadow Translation Look-Aside Buffer Size
4
C_MMU_ITLB_SIZE
Instruction Shadow Translation Look-Aside Buffer Size
2
C_MMU_TLB_ACCESS
Enable Access to Memory Management Special Registers
3
C_MMU_ZONES
Number of Memory Protection Zones
16
C_NUMBER_OF_PC_BRK
Number of PC Breakpoints
1
C_NUMBER_OF_RD_ADDR_BRK
Number of Read Address Watchpoints
0
C_NUMBER_OF_WR_ADDR_BRK
Number of Write Address Watchpoints
0
C_OPCODE_0x0_ILLEGAL
<qt>Generate Illegal Instruction Exception for NULL Instruction</qt>
0
C_PVR
Specifies Processor Version Register
0
C_PVR_USER1
Specify USER1 Bits in Processor Version Register
0x00
C_PVR_USER2
Specify USER2 Bits in Processor Version Registers
0x00000000
C_RESET_MSR
Specify Reset Value for Select MSR Bits
0x00000000
C_SCO
C_SCO
0
C_UNALIGNED_EXCEPTIONS
Enable Unaligned Data Exception
0
C_USE_BARREL
Enable Barrel Shifter
0
C_USE_DCACHE
Enable Data Cache
0
C_USE_DIV
Enable Integer Divider
0
C_USE_EXTENDED_FSL_INSTR
Enable Additional FSL Instructions
0
C_USE_EXT_BRK
Enable External Break handling
1
C_USE_EXT_NM_BRK
Enable External Non-maskable Break handling
1
C_USE_FPU
Enable Floating Point Unit
0
C_USE_HW_MUL
Enable Integer Multiplier
1
C_USE_ICACHE
Enable Instruction Cache
0
C_USE_INTERRUPT
Enable Interrupt handling
0
C_USE_MMU
Memory Management
0
C_USE_MSR_INSTR
Enable Additional Machine Status Register Instructions
1
C_USE_PCMP_INSTR
Enable Pattern Comparator
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 714 5888 12
Slice Flip Flops 898 11776 7
4 input LUTs 1389 11776 11
IOs 2432 NA NA
bonded IOBs 0 372 0
MULT18X18SIOs 3 20 15





Busses TOP
dlmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'


dlmb IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 LMB_Clk I 1 sys_clk_s
2 SYS_Rst I 1 sys_bus_reset
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 DLMB
SLAVE dlmb_cntlr SLMB


General
IP Core lmb_v10
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH
Active High External Reset
1
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_LMB_NUM_SLAVES
Number of Bus Slaves
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 5888 0
Slice Flip Flops 1 11776 0
4 input LUTs 1 11776 0
IOs 211 NA NA
bonded IOBs 0 372 0


ilmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'


ilmb IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 LMB_Clk I 1 sys_clk_s
2 SYS_Rst I 1 sys_bus_reset
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 ILMB
SLAVE ilmb_cntlr SLMB


General
IP Core lmb_v10
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH
Active High External Reset
1
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_LMB_NUM_SLAVES
Number of Bus Slaves
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 5888 0
Slice Flip Flops 1 11776 0
4 input LUTs 1 11776 0
IOs 211 NA NA
bonded IOBs 0 372 0


mb_plb   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'


mb_plb IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 PLB_Clk I 1 sys_clk_s
2 SYS_Rst I 1 sys_bus_reset
Bus Connections
TYPE NAME BIF
MASTER vga_16bit_plbv46_0 MPLB
MASTER microblaze_0 DPLB
MASTER microblaze_0 IPLB
MASTER vdec1_plbv46_0 MPLB
SLAVE xps_iic_0 SPLB
SLAVE vga_16bit_plbv46_0 SPLB
SLAVE debug_module SPLB
SLAVE RS232_DTE SPLB
SLAVE RS232_DCE SPLB
SLAVE DDR2_SDRAM SPLB0
SLAVE vdec1_plbv46_0 SPLB


General
IP Core plb_v46
Version 1.03.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3a
C_BASEADDR
Base Address
0b1111111111
C_HIGHADDR
High Address
0b0000000000
C_ADDR_PIPELINING_TYPE
Enable Address Pipelining Type
1
C_ARB_TYPE
Selects the Arbitration Scheme
0
C_DCR_AWIDTH
DCR Address Bus Width
10
C_DCR_DWIDTH
DCR Data Bus Width
32
C_DCR_INTFCE
Include DCR Interface and Error Registers
0
C_EXT_RESET_HIGH
External Reset Active High
1
 
Name Value
C_IRQ_ACTIVE
IRQ Active State
1
C_NUM_CLK_PLB2OPB_REARB
<qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt>
5
C_P2P
Optimize PLB for Point-to-point Topology
0
C_PLBV46_AWIDTH
PLB Address Bus Width
32
C_PLBV46_DWIDTH
PLB Data Bus Width
64
C_PLBV46_MID_WIDTH
PLB Master ID Bus Width
2
C_PLBV46_NUM_MASTERS
Number of PLB Masters
4
C_PLBV46_NUM_SLAVES
Number of PLB Slaves
7
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 523 5888 8
Slice Flip Flops 183 11776 1
4 input LUTs 768 11776 6
IOs 2045 NA NA
bonded IOBs 0 372 0





Memory TOP
lmb_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.


lmb_bram IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
TARGET PORTA XIL ilmb_port ilmb_cntlr
TARGET PORTB XIL dlmb_port dlmb_cntlr


General
IP Core bram_block
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3a
C_MEMSIZE
Size of BRAM(s) in Bytes
0x2000
C_NUM_WE
Number of Byte Write Enables
4
C_PORT_AWIDTH
Address Width of Port A and B
32
C_PORT_DWIDTH
Data Width of Port A and B
32
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 0 5888 0
IOs 206 NA NA
bonded IOBs 0 372 0
BRAMs 4 20 20





Memory Controllers TOP
DDR2_SDRAM   Multi-Port Memory Controller(DDR/DDR2/SDRAM)
Multi-port memory controller.


DDR2_SDRAM IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 DDR2_DQS_Div_I I 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I
2 MPMC_Clk0 I 1 DDR2_SDRAM_mpmc_clk_s
3 MPMC_Clk90 I 1 DDR2_SDRAM_mpmc_clk_90_s
4 MPMC_Rst I 1 sys_periph_reset
5 DDR2_DQS IO 0:1 fpga_0_DDR2_SDRAM_DDR2_DQS
6 DDR2_DQS_n IO 0:1 fpga_0_DDR2_SDRAM_DDR2_DQS_n
7 DDR2_DQ IO 0:15 fpga_0_DDR2_SDRAM_DDR2_DQ
8 DDR2_ODT O 1 fpga_0_DDR2_SDRAM_DDR2_ODT
9 DDR2_Addr O 0:12 fpga_0_DDR2_SDRAM_DDR2_Addr
10 DDR2_BankAddr O 0:1 fpga_0_DDR2_SDRAM_DDR2_BankAddr
11 DDR2_CAS_n O 1 fpga_0_DDR2_SDRAM_DDR2_CAS_n
12 DDR2_RAS_n O 1 fpga_0_DDR2_SDRAM_DDR2_RAS_n
13 DDR2_CE O 1 fpga_0_DDR2_SDRAM_DDR2_CE
14 DDR2_CS_n O 1 fpga_0_DDR2_SDRAM_DDR2_CS_n
15 DDR2_WE_n O 1 fpga_0_DDR2_SDRAM_DDR2_WE_n
16 DDR2_Clk O 1 fpga_0_DDR2_SDRAM_DDR2_Clk
17 DDR2_Clk_n O 1 fpga_0_DDR2_SDRAM_DDR2_Clk_n
18 DDR2_DM O 0:1 fpga_0_DDR2_SDRAM_DDR2_DM
19 DDR2_DQS_Div_O O 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
SLAVE SPLB0 PLBV46 mb_plb xps_iic_0


General
IP Core mpmc
Version 4.03.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY spartan3a
C_MPMC_BASEADDR
Base Addr
0x8C000000
C_MPMC_CTRL_BASEADDR
Control Base Addr
0xFFFFFFFF
C_MPMC_CTRL_HIGHADDR
Control High Addr
0x00000000
C_MPMC_HIGHADDR
High Addr
0x8FFFFFFF
C_PIM0_BASEADDR
0xFFFFFFFF
C_PIM0_HIGHADDR
0x00000000
C_PIM1_BASEADDR
0xFFFFFFFF
C_PIM1_HIGHADDR
0x00000000
C_PIM2_BASEADDR
0xFFFFFFFF
C_PIM2_HIGHADDR
0x00000000
C_PIM3_BASEADDR
0xFFFFFFFF
C_PIM3_HIGHADDR
0x00000000
C_PIM4_BASEADDR
0xFFFFFFFF
C_PIM4_HIGHADDR
0x00000000
C_PIM5_BASEADDR
0xFFFFFFFF
C_PIM5_HIGHADDR
0x00000000
C_PIM6_BASEADDR
0xFFFFFFFF
C_PIM6_HIGHADDR
0x00000000
C_PIM7_BASEADDR
0xFFFFFFFF
C_PIM7_HIGHADDR
0x00000000
C_SDMA_CTRL0_BASEADDR
0xFFFFFFFF
C_SDMA_CTRL0_HIGHADDR
0x00000000
C_SDMA_CTRL1_BASEADDR
0xFFFFFFFF
C_SDMA_CTRL1_HIGHADDR
0x00000000
C_SDMA_CTRL2_BASEADDR
0xFFFFFFFF
C_SDMA_CTRL2_HIGHADDR
0x00000000
C_SDMA_CTRL3_BASEADDR
0xFFFFFFFF
C_SDMA_CTRL3_HIGHADDR
0x00000000
C_SDMA_CTRL4_BASEADDR
0xFFFFFFFF
C_SDMA_CTRL4_HIGHADDR
0x00000000
C_SDMA_CTRL5_BASEADDR
0xFFFFFFFF
C_SDMA_CTRL5_HIGHADDR
0x00000000
C_SDMA_CTRL6_BASEADDR
0xFFFFFFFF
C_SDMA_CTRL6_HIGHADDR
0x00000000
C_SDMA_CTRL7_BASEADDR
0xFFFFFFFF
C_SDMA_CTRL7_HIGHADDR
0x00000000
C_SDMA_CTRL_BASEADDR
SDMA Register Base Address
0xFFFFFFFF
C_SDMA_CTRL_HIGHADDR
SDMA High Address
0x00000000
C_ALL_PIMS_SHARE_ADDRESSES
Use Common Base Addr
1
C_ARB0_ALGO
<qt><b>Select Arbitration Algorithm</b></qt>
ROUND_ROBIN
C_ARB0_NUM_SLOTS
Number of Time Slots
8
C_ARB0_SLOT0
Time Slot 0
01234567
C_ARB0_SLOT1
Time Slot 1
12345670
C_ARB0_SLOT10
Time Slot 10
23456701
C_ARB0_SLOT11
Time Slot 11
34567012
C_ARB0_SLOT12
Time Slot 12
45670123
C_ARB0_SLOT13
Time Slot 13
56701234
C_ARB0_SLOT14
Time Slot 14
67012345
C_ARB0_SLOT15
Time Slot 15
70123456
C_ARB0_SLOT2
Time Slot 2
23456701
C_ARB0_SLOT3
Time Slot 3
34567012
C_ARB0_SLOT4
Time Slot 4
45670123
C_ARB0_SLOT5
Time Slot 5
56701234
C_ARB0_SLOT6
Time Slot 6
67012345
C_ARB0_SLOT7
Time Slot 7
70123456
C_ARB0_SLOT8
Time Slot 8
01234567
C_ARB0_SLOT9
Time Slot 9
12345670
C_ARB_BRAM_INIT_00 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000
C_ARB_BRAM_INIT_01 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_02 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000
C_ARB_BRAM_INIT_03 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_04 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000
C_ARB_BRAM_INIT_05 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_06 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000
C_ARB_BRAM_INIT_07 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_PIPELINE
Turn on Arbiter Pipeline
1
C_ARB_USE_DEFAULT 0
C_B16_REPEAT_CNT 0
C_B32_REPEAT_CNT 6
C_B64_REPEAT_CNT 14
C_BASEADDR_CTRL0 0x000
C_BASEADDR_CTRL1 0x00F
C_BASEADDR_CTRL10 0x0A6
C_BASEADDR_CTRL11 0x0BB
C_BASEADDR_CTRL12 0x0CA
C_BASEADDR_CTRL13 0x0DF
C_BASEADDR_CTRL14 0x0EE
C_BASEADDR_CTRL15 0x101
C_BASEADDR_CTRL2 0x019
C_BASEADDR_CTRL3 0x028
C_BASEADDR_CTRL4 0x032
C_BASEADDR_CTRL5 0x043
C_BASEADDR_CTRL6 0x04E
C_BASEADDR_CTRL7 0x063
C_BASEADDR_CTRL8 0x072
C_BASEADDR_CTRL9 0x08F
C_CTRL_AP_COL_DELAY 0x1
C_CTRL_AP_PIPELINE1_CE_DELAY 0x0
C_CTRL_AP_PI_ADDR_CE_DELAY 0x0
C_CTRL_AP_PORT_SELECT_DELAY 0x0
C_CTRL_BRAM_INITP_00 0x0000111110000000000000000000000111110000000000000000000011111100
C_CTRL_BRAM_INITP_01 0x0000000000000000000000000000000000001111100000000000000000000000
C_CTRL_BRAM_INITP_02 0x2000000000001111100002000000000000000000000000000000000011111000
C_CTRL_BRAM_INITP_03 0x0000000000000000000000000000200000000000111110000200000000000000
C_CTRL_BRAM_INITP_04 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_05 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_06 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_07 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INIT_00 0x0001003C0001003C0001003C0001003C000100240001913C0001813C00018038
C_CTRL_BRAM_INIT_01 0x000080380001003C0001003C0001003C0001003C000140280001003D0001003C
C_CTRL_BRAM_INIT_02 0x0000003C0000003C000040280000003C0000003D000000340000943C0000803C
C_CTRL_BRAM_INIT_03 0x0001003C0001003C0001003C000100240001913C0001813C000180380000003C
C_CTRL_BRAM_INIT_04 0x0001003C0001003C0001003C0001003C000140280001003D0001003C0001003C
C_CTRL_BRAM_INIT_05 0x0000003C000040280000003C0000003D000004340000943C0000803C00008038
C_CTRL_BRAM_INIT_06 0x000100240001213C000101240001913C0001813C000180380000003C0000003C
C_CTRL_BRAM_INIT_07 0x0001003C000140280001003D0001003C0001003C0001003C0001003C0001003C
C_CTRL_BRAM_INIT_08 0x0000243C000004340000943C0000803C000080380001003C0001003C0001003C
C_CTRL_BRAM_INIT_09 0x0001813C000180380000003C0000003C0000003C000040280000003C00000435
C_CTRL_BRAM_INIT_0A 0x000100240001213C000101240001213C000101240001213C000101240001913C
C_CTRL_BRAM_INIT_0B 0x0001003C000140280001003D0001003C0001003C0001003C0001003C0001003C
C_CTRL_BRAM_INIT_0C 0x0000243C000004340000943C0000803C000080380001003C0001003C0001003C
C_CTRL_BRAM_INIT_0D 0x0000003C000040280000003C000004350000243C000004340000243C00000434
C_CTRL_BRAM_INIT_0E 0x000101240001213C000101240001913C0001813C000180380000003C0000003C
C_CTRL_BRAM_INIT_0F 0x000101240001213C000101240001213C000101240001213C000101240001213C
C_CTRL_BRAM_INIT_10 0x0001003C0001003C0001003C0001003C000100240001213C000101240001213C
C_CTRL_BRAM_INIT_11 0x000080380001003C0001003C0001003C0001003C000140280001003D0001003C
C_CTRL_BRAM_INIT_12 0x0000243C000004340000243C000004340000243C000004340000943C0000803C
C_CTRL_BRAM_INIT_13 0x0000243C000004340000243C000004340000243C000004340000243C00000434
C_CTRL_BRAM_INIT_14 0x0001813C000180380000003C0000003C0000003C000040280000003C00000435
C_CTRL_BRAM_INIT_15 0x000100240001213C000101240001213C000101240001213C000101240001913C
C_CTRL_BRAM_INIT_16 0x0001003C000140280001003D0001003C0001003C0001003C0001003C0001003C
C_CTRL_BRAM_INIT_17 0x0000243C000004340000943C0000803C000080380001003C0001003C0001003C
C_CTRL_BRAM_INIT_18 0x0000003C000040280000003C000004350000243C000004340000243C00000434
C_CTRL_BRAM_INIT_19 0x000101240001213C000101240001913C0001813C000180380000003C0000003C
C_CTRL_BRAM_INIT_1A 0x0001003C0001003C0001003C0001003C000100240001213C000101240001213C
C_CTRL_BRAM_INIT_1B 0x000080380001003C0001003C0001003C0001003C000140280001003D0001003C
C_CTRL_BRAM_INIT_1C 0x0000243C000004340000243C000004340000243C000004340000943C0000803C
C_CTRL_BRAM_INIT_1D 0x0000003C000040280000003C0000003C0000003C000040280000003C00000435
C_CTRL_BRAM_INIT_1E 0x0000003C0000003C0000003C0000003C0000003C000000300000003C0000003C
C_CTRL_BRAM_INIT_1F 0x0000003C0000003C0000003C0000003C0000003D0000003C0000003C0000003C
C_CTRL_BRAM_INIT_20 0x000002FC000002FC000002FC000002FC000002FC0000003C0000003C0000003C
C_CTRL_BRAM_INIT_21 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_22 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_23 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_24 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_25 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_26 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_27 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_28 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_29 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2A 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2B 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2C 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2D 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2E 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2F 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_30 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_31 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_32 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_33 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_34 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_35 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_36 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_37 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_38 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_39 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3A 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3B 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3C 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3D 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3E 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3F 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_SRVAL 0x0000002FC
C_CTRL_DP_LOAD_RDWDADDR_DELAY 0x2
C_CTRL_DP_RDFIFO_WHICHPORT_DELAY 0xC
C_CTRL_DP_SIZE_DELAY 0x2
C_CTRL_DP_WRFIFO_WHICHPORT_DELAY 0x4
C_CTRL_PHYIF_DUMMYREADSTART_DELAY 0x5
C_CTRL_Q0_DELAY 0x1
C_CTRL_Q10_DELAY 0x1
C_CTRL_Q11_DELAY 0x2
C_CTRL_Q12_DELAY 0x1
C_CTRL_Q13_DELAY 0x1
C_CTRL_Q14_DELAY 0x1
C_CTRL_Q15_DELAY 0x1
C_CTRL_Q16_DELAY 0x1
C_CTRL_Q17_DELAY 0x0
C_CTRL_Q18_DELAY 0x0
C_CTRL_Q19_DELAY 0x0
C_CTRL_Q1_DELAY 0x0
C_CTRL_Q20_DELAY 0x0
C_CTRL_Q21_DELAY 0x0
C_CTRL_Q22_DELAY 0x0
C_CTRL_Q23_DELAY 0x0
C_CTRL_Q24_DELAY 0x0
C_CTRL_Q25_DELAY 0x0
C_CTRL_Q26_DELAY 0x0
C_CTRL_Q27_DELAY 0x0
C_CTRL_Q28_DELAY 0x0
C_CTRL_Q29_DELAY 0x0
C_CTRL_Q2_DELAY 0x2
C_CTRL_Q30_DELAY 0x0
C_CTRL_Q31_DELAY 0x0
C_CTRL_Q32_DELAY 0x2
C_CTRL_Q33_DELAY 0x1
C_CTRL_Q34_DELAY 0x0
C_CTRL_Q35_DELAY 0x0
C_CTRL_Q3_DELAY 0x2
C_CTRL_Q4_DELAY 0x2
C_CTRL_Q5_DELAY 0x2
C_CTRL_Q6_DELAY 0x5
C_CTRL_Q7_DELAY 0x2
C_CTRL_Q8_DELAY 0x1
C_CTRL_Q9_DELAY 0x2
C_DDR2_DQSN_ENABLE
Enable DQSN in DDR2
1
C_DEBUG_REG_ENABLE
Enable Debug Registers
0
C_ECC_DATA_WIDTH 0
C_ECC_DEC_THRESHOLD
<qt>DEC Threshold</qt>
1
C_ECC_DEFAULT_ON
ECC Default is On
1
C_ECC_DM_WIDTH 0
C_ECC_DQS_WIDTH 0
C_ECC_PEC_THRESHOLD
<qt>PEC Threshold</qt>
1
C_ECC_SEC_THRESHOLD
SEC Threshold
1
C_HIGHADDR_CTRL0 0x00E
C_HIGHADDR_CTRL1 0x018
C_HIGHADDR_CTRL10 0x0BA
C_HIGHADDR_CTRL11 0x0C9
C_HIGHADDR_CTRL12 0x0DE
C_HIGHADDR_CTRL13 0x0ED
C_HIGHADDR_CTRL14 0x100
C_HIGHADDR_CTRL15 0x102
C_HIGHADDR_CTRL2 0x027
C_HIGHADDR_CTRL3 0x031
C_HIGHADDR_CTRL4 0x042
C_HIGHADDR_CTRL5 0x04D
C_HIGHADDR_CTRL6 0x062
C_HIGHADDR_CTRL7 0x071
C_HIGHADDR_CTRL8 0x08E
C_HIGHADDR_CTRL9 0x0A5
C_IDELAYCTRL_LOC
IDELAYCTRL Constraint Locations (Hyphen separated)
NOT_SET
C_INCLUDE_ECC_SUPPORT
Enable ECC
0
C_INCLUDE_ECC_TEST
Include ECC Test
0
C_MAX_REQ_ALLOWED
Number of Requests MPMC can Queue per Port
1
C_MEM_ADDR_WIDTH
Memory Addr Width
13
C_MEM_BANKADDR_WIDTH
<qt>Memory Bank Addr Width</qt>
2
C_MEM_BITS_DATA_PER_DQS 8
C_MEM_CAS_LATENCY0 3
C_MEM_CE_WIDTH
CE Width
1
C_MEM_CLK_WIDTH
Clock Width
1
C_MEM_CS_N_WIDTH
CSn Width
1
C_MEM_DATA_WIDTH
Memory Data Width
16
C_MEM_DM_WIDTH
Memory DM Width
2
C_MEM_DQS_IO_COL
C_MEM_DQS_IO_COL
0x000000000000000000
C_MEM_DQS_WIDTH
Memory DQS Width
2
C_MEM_DQ_IO_MS
C_MEM_DQ_IO_MS
0x000000000000000000
C_MEM_NUM_DIMMS
Number of DIMMs
1
C_MEM_NUM_RANKS
No. of Ranks
1
C_MEM_ODT_TYPE
ODT Setting
0
C_MEM_ODT_WIDTH
ODT Width
1
C_MEM_PARTNO
Part No.
MT47H32M16-3
C_MEM_PART_CAS_A
<qt>CAS Latency A</qt>
3
C_MEM_PART_CAS_A_FMAX
<qt>CAS Latency A Fmax</qt>
200
C_MEM_PART_CAS_B
<qt>CAS Latency B</qt>
4
C_MEM_PART_CAS_B_FMAX
<qt>CAS Latency B Fmax</qt>
266
C_MEM_PART_CAS_C
<qt>CAS Latency C</qt>
5
C_MEM_PART_CAS_C_FMAX
<qt>CAS Latency C Fmax</qt>
333
C_MEM_PART_CAS_D
<qt>CAS Latency D</qt>
0
C_MEM_PART_CAS_D_FMAX
<qt>CAS Latency D Fmax</qt>
0
C_MEM_PART_DATA_DEPTH
Data Depth
32
C_MEM_PART_DATA_WIDTH
Data Width
16
C_MEM_PART_NUM_BANK_BITS
Bank Bits
2
C_MEM_PART_NUM_COL_BITS
Column Bits
10
C_MEM_PART_NUM_ROW_BITS
Row Bits
13
C_MEM_PART_TAL 0
C_MEM_PART_TCCD
tCCD
2
C_MEM_PART_TDQSS 1
C_MEM_PART_TMRD
tMRD (ps)
2
C_MEM_PART_TRAS
tRAS (ps)
40000
C_MEM_PART_TRASMAX
tRASMAX (ps)
70000000
C_MEM_PART_TRC
tRC (ps)
55000
C_MEM_PART_TRCD
tRCD (ps)
15000
C_MEM_PART_TREFI
tREFI (ps)
7800000
C_MEM_PART_TRFC
tRFC (ps)
105000
C_MEM_PART_TRP
tRP (ps)
15000
C_MEM_PART_TRRD
tRRD (ps)
10000
C_MEM_PART_TRTP 7500
C_MEM_PART_TWR
tWR (ps)
15000
C_MEM_PART_TWTR
tWTR (ps)
7500
C_MEM_REDUCED_DRV
<qt>Reduced Drive Output</qt>
0
C_MEM_REG_DIMM
Registered Memory
0
C_MEM_TYPE
Type
DDR2
C_MPMC_CLK0_PERIOD_PS
<qt>Memory Clock Period (ps)</qt>
7499
C_MPMC_CTRL_AWIDTH 32
C_MPMC_CTRL_DWIDTH 64
C_MPMC_CTRL_MID_WIDTH 1
C_MPMC_CTRL_NATIVE_DWIDTH 32
C_MPMC_CTRL_NUM_MASTERS 1
C_MPMC_CTRL_P2P 1
C_MPMC_CTRL_SMALLEST_MASTER 32
C_MPMC_CTRL_SUPPORT_BURSTS 0
C_NUM_IDELAYCTRL
Number of IDELAYCTRL Elements
1
C_NUM_PORTS
C_NUM_PORTS
1
C_PI0_ADDRACK_PIPELINE
1
C_PI0_PM_DC_CNTR
1
C_PI0_PM_USED
1
C_PI0_RD_FIFO_APP_PIPELINE
1
C_PI0_RD_FIFO_MEM_PIPELINE
1
C_PI0_RD_FIFO_TYPE BRAM
C_PI0_WR_FIFO_APP_PIPELINE
1
C_PI0_WR_FIFO_MEM_PIPELINE
1
C_PI0_WR_FIFO_TYPE BRAM
C_PI1_ADDRACK_PIPELINE
1
C_PI1_PM_DC_CNTR
1
C_PI1_PM_USED
1
C_PI1_RD_FIFO_APP_PIPELINE
1
C_PI1_RD_FIFO_MEM_PIPELINE
1
C_PI1_RD_FIFO_TYPE BRAM
C_PI1_WR_FIFO_APP_PIPELINE
1
C_PI1_WR_FIFO_MEM_PIPELINE
1
C_PI1_WR_FIFO_TYPE BRAM
C_PI2_ADDRACK_PIPELINE
1
C_PI2_PM_DC_CNTR
1
C_PI2_PM_USED
1
C_PI2_RD_FIFO_APP_PIPELINE
1
C_PI2_RD_FIFO_MEM_PIPELINE
1
C_PI2_RD_FIFO_TYPE BRAM
C_PI2_WR_FIFO_APP_PIPELINE
1
C_PI2_WR_FIFO_MEM_PIPELINE
1
C_PI2_WR_FIFO_TYPE BRAM
C_PI3_ADDRACK_PIPELINE
1
C_PI3_PM_DC_CNTR
1
C_PI3_PM_USED
1
C_PI3_RD_FIFO_APP_PIPELINE
1
C_PI3_RD_FIFO_MEM_PIPELINE
1
C_PI3_RD_FIFO_TYPE BRAM
C_PI3_WR_FIFO_APP_PIPELINE
1
C_PI3_WR_FIFO_MEM_PIPELINE
1
C_PI3_WR_FIFO_TYPE BRAM
C_PI4_ADDRACK_PIPELINE
1
 
Name Value
C_PI4_PM_DC_CNTR
1
C_PI4_PM_USED
1
C_PI4_RD_FIFO_APP_PIPELINE
1
C_PI4_RD_FIFO_MEM_PIPELINE
1
C_PI4_RD_FIFO_TYPE BRAM
C_PI4_WR_FIFO_APP_PIPELINE
1
C_PI4_WR_FIFO_MEM_PIPELINE
1
C_PI4_WR_FIFO_TYPE BRAM
C_PI5_ADDRACK_PIPELINE
1
C_PI5_PM_DC_CNTR
1
C_PI5_PM_USED
1
C_PI5_RD_FIFO_APP_PIPELINE
1
C_PI5_RD_FIFO_MEM_PIPELINE
1
C_PI5_RD_FIFO_TYPE BRAM
C_PI5_WR_FIFO_APP_PIPELINE
1
C_PI5_WR_FIFO_MEM_PIPELINE
1
C_PI5_WR_FIFO_TYPE BRAM
C_PI6_ADDRACK_PIPELINE
1
C_PI6_PM_DC_CNTR
1
C_PI6_PM_USED
1
C_PI6_RD_FIFO_APP_PIPELINE
1
C_PI6_RD_FIFO_MEM_PIPELINE
1
C_PI6_RD_FIFO_TYPE BRAM
C_PI6_WR_FIFO_APP_PIPELINE
1
C_PI6_WR_FIFO_MEM_PIPELINE
1
C_PI6_WR_FIFO_TYPE BRAM
C_PI7_ADDRACK_PIPELINE
1
C_PI7_PM_DC_CNTR
1
C_PI7_PM_USED
1
C_PI7_RD_FIFO_APP_PIPELINE
1
C_PI7_RD_FIFO_MEM_PIPELINE
1
C_PI7_RD_FIFO_TYPE BRAM
C_PI7_WR_FIFO_APP_PIPELINE
1
C_PI7_WR_FIFO_MEM_PIPELINE
1
C_PI7_WR_FIFO_TYPE BRAM
C_PIM0_BASETYPE
2
C_PIM0_DATA_WIDTH
NPI Width
64
C_PIM0_OFFSET
0x00000000
C_PIM0_SUBTYPE PLB
C_PIM1_BASETYPE
0
C_PIM1_DATA_WIDTH
NPI Width
64
C_PIM1_OFFSET
0x00000000
C_PIM1_SUBTYPE INACTIVE
C_PIM2_BASETYPE
0
C_PIM2_DATA_WIDTH
NPI Width
64
C_PIM2_OFFSET
0x00000000
C_PIM2_SUBTYPE INACTIVE
C_PIM3_BASETYPE
0
C_PIM3_DATA_WIDTH
NPI Width
64
C_PIM3_OFFSET
0x00000000
C_PIM3_SUBTYPE INACTIVE
C_PIM4_BASETYPE
0
C_PIM4_DATA_WIDTH
NPI Width
64
C_PIM4_OFFSET
0x00000000
C_PIM4_SUBTYPE INACTIVE
C_PIM5_BASETYPE
0
C_PIM5_DATA_WIDTH
NPI Width
64
C_PIM5_OFFSET
0x00000000
C_PIM5_SUBTYPE INACTIVE
C_PIM6_BASETYPE
0
C_PIM6_DATA_WIDTH
NPI Width
64
C_PIM6_OFFSET
0x00000000
C_PIM6_SUBTYPE INACTIVE
C_PIM7_BASETYPE
0
C_PIM7_DATA_WIDTH
NPI Width
64
C_PIM7_OFFSET
0x00000000
C_PIM7_SUBTYPE INACTIVE
C_PM_DC_WIDTH
<qt>Dead Cycle Counter Width</qt>
48
C_PM_ENABLE
Enable Performance Monitor
0
C_PM_GC_CNTR
<qt>Enable Global Cycle Counter</qt>
1
C_PM_GC_WIDTH
<qt>Global Cycle Counter Width</qt>
48
C_PM_SHIFT_CNT_BY
<qt>Shift Value of Trans Counter</qt>
1
C_PPC440MC0_BURST_LENGTH
Burst Length
4
C_PPC440MC0_PIPE_STAGES
Pipe Stage
1
C_PPC440MC1_BURST_LENGTH
Burst Length
4
C_PPC440MC1_PIPE_STAGES
Pipe Stage
1
C_PPC440MC2_BURST_LENGTH
Burst Length
4
C_PPC440MC2_PIPE_STAGES
Pipe Stage
1
C_PPC440MC3_BURST_LENGTH
Burst Length
4
C_PPC440MC3_PIPE_STAGES
Pipe Stage
1
C_PPC440MC4_BURST_LENGTH
Burst Length
4
C_PPC440MC4_PIPE_STAGES
Pipe Stage
1
C_PPC440MC5_BURST_LENGTH
Burst Length
4
C_PPC440MC5_PIPE_STAGES
Pipe Stage
1
C_PPC440MC6_BURST_LENGTH
Burst Length
4
C_PPC440MC6_PIPE_STAGES
Pipe Stage
1
C_PPC440MC7_BURST_LENGTH
Burst Length
4
C_PPC440MC7_PIPE_STAGES
Pipe Stage
1
C_RD_DATAPATH_TML_MAX_FANOUT
Read Pipeline Max Fanout
0
C_SDMA0_COMPLETED_ERR_RX
Enable Completed Err on RX
1
C_SDMA0_COMPLETED_ERR_TX
Enable TX Completed Err
1
C_SDMA0_PI2LL_CLK_RATIO
MPMC to SDMA Clk Ratio
1
C_SDMA0_PRESCALAR
Clock Div. of Int. Timer Clk
1023
C_SDMA1_COMPLETED_ERR_RX
Enable Completed Err on RX
1
C_SDMA1_COMPLETED_ERR_TX
Enable Completed Err on TX
1
C_SDMA1_PI2LL_CLK_RATIO
MPMC to SDMA Clk Ratio
1
C_SDMA1_PRESCALAR
Clock Div. of Int. Timer Clk
1023
C_SDMA2_COMPLETED_ERR_RX
Enable Completed Err on RX
1
C_SDMA2_COMPLETED_ERR_TX
Enable Completed Err on TX
1
C_SDMA2_PI2LL_CLK_RATIO
MPMC to SDMA Clk Ratio
1
C_SDMA2_PRESCALAR
Clock Div. of Int. Timer Clk
1023
C_SDMA3_COMPLETED_ERR_RX
Enable Completed Err on RX
1
C_SDMA3_COMPLETED_ERR_TX
Enable Completed Err on TX
1
C_SDMA3_PI2LL_CLK_RATIO
MPMC to SDMA Clk Ratio
1
C_SDMA3_PRESCALAR
Clock Div. of Int. Timer Clk
1023
C_SDMA4_COMPLETED_ERR_RX
Enable Completed Err on RX
1
C_SDMA4_COMPLETED_ERR_TX
Enable Completed Err on TX
1
C_SDMA4_PI2LL_CLK_RATIO
MPMC to SDMA Clk Ratio
1
C_SDMA4_PRESCALAR
Clock Div. of Int. Timer Clk
1023
C_SDMA5_COMPLETED_ERR_RX
Enable Completed Err on RX
1
C_SDMA5_COMPLETED_ERR_TX
Enable Completed Err on TX
1
C_SDMA5_PI2LL_CLK_RATIO
MPMC to SDMA Clk Ratio
1
C_SDMA5_PRESCALAR
Clock Div. of Int. Timer Clk
1023
C_SDMA6_COMPLETED_ERR_RX
Enable Completed Err on RX
1
C_SDMA6_COMPLETED_ERR_TX
Enable Completed Err on TX
1
C_SDMA6_PI2LL_CLK_RATIO
MPMC to SDMA Clk Ratio
1
C_SDMA6_PRESCALAR
Clock Div. of Int. Timer Clk
1023
C_SDMA7_COMPLETED_ERR_RX
Enable Completed Err on RX
1
C_SDMA7_COMPLETED_ERR_TX
Enable Completed Err on TX
1
C_SDMA7_PI2LL_CLK_RATIO
MPMC to SDMA Clk Ratio
1
C_SDMA7_PRESCALAR
Clock Div. of Int. Timer Clk
1023
C_SDMA_CTRL0_AWIDTH 32
C_SDMA_CTRL0_DWIDTH 64
C_SDMA_CTRL0_MID_WIDTH 1
C_SDMA_CTRL0_NATIVE_DWIDTH 32
C_SDMA_CTRL0_NUM_MASTERS 1
C_SDMA_CTRL0_P2P 1
C_SDMA_CTRL0_SMALLEST_MASTER 32
C_SDMA_CTRL0_SUPPORT_BURSTS 0
C_SDMA_CTRL1_AWIDTH 32
C_SDMA_CTRL1_DWIDTH 64
C_SDMA_CTRL1_MID_WIDTH 1
C_SDMA_CTRL1_NATIVE_DWIDTH 32
C_SDMA_CTRL1_NUM_MASTERS 1
C_SDMA_CTRL1_P2P 1
C_SDMA_CTRL1_SMALLEST_MASTER 32
C_SDMA_CTRL1_SUPPORT_BURSTS 0
C_SDMA_CTRL2_AWIDTH 32
C_SDMA_CTRL2_DWIDTH 64
C_SDMA_CTRL2_MID_WIDTH 1
C_SDMA_CTRL2_NATIVE_DWIDTH 32
C_SDMA_CTRL2_NUM_MASTERS 1
C_SDMA_CTRL2_P2P 1
C_SDMA_CTRL2_SMALLEST_MASTER 32
C_SDMA_CTRL2_SUPPORT_BURSTS 0
C_SDMA_CTRL3_AWIDTH 32
C_SDMA_CTRL3_DWIDTH 64
C_SDMA_CTRL3_MID_WIDTH 1
C_SDMA_CTRL3_NATIVE_DWIDTH 32
C_SDMA_CTRL3_NUM_MASTERS 1
C_SDMA_CTRL3_P2P 1
C_SDMA_CTRL3_SMALLEST_MASTER 32
C_SDMA_CTRL3_SUPPORT_BURSTS 0
C_SDMA_CTRL4_AWIDTH 32
C_SDMA_CTRL4_DWIDTH 64
C_SDMA_CTRL4_MID_WIDTH 1
C_SDMA_CTRL4_NATIVE_DWIDTH 32
C_SDMA_CTRL4_NUM_MASTERS 1
C_SDMA_CTRL4_P2P 1
C_SDMA_CTRL4_SMALLEST_MASTER 32
C_SDMA_CTRL4_SUPPORT_BURSTS 0
C_SDMA_CTRL5_AWIDTH 32
C_SDMA_CTRL5_DWIDTH 64
C_SDMA_CTRL5_MID_WIDTH 1
C_SDMA_CTRL5_NATIVE_DWIDTH 32
C_SDMA_CTRL5_NUM_MASTERS 1
C_SDMA_CTRL5_P2P 1
C_SDMA_CTRL5_SMALLEST_MASTER 32
C_SDMA_CTRL5_SUPPORT_BURSTS 0
C_SDMA_CTRL6_AWIDTH 32
C_SDMA_CTRL6_DWIDTH 64
C_SDMA_CTRL6_MID_WIDTH 1
C_SDMA_CTRL6_NATIVE_DWIDTH 32
C_SDMA_CTRL6_NUM_MASTERS 1
C_SDMA_CTRL6_P2P 1
C_SDMA_CTRL6_SMALLEST_MASTER 32
C_SDMA_CTRL6_SUPPORT_BURSTS 0
C_SDMA_CTRL7_AWIDTH 32
C_SDMA_CTRL7_DWIDTH 64
C_SDMA_CTRL7_MID_WIDTH 1
C_SDMA_CTRL7_NATIVE_DWIDTH 32
C_SDMA_CTRL7_NUM_MASTERS 1
C_SDMA_CTRL7_P2P 1
C_SDMA_CTRL7_SMALLEST_MASTER 32
C_SDMA_CTRL7_SUPPORT_BURSTS 0
C_SKIP_1_VALUE 0x001
C_SKIP_2_VALUE 0x001
C_SKIP_3_VALUE 0x001
C_SKIP_4_VALUE 0x001
C_SKIP_5_VALUE 0x001
C_SKIP_6_VALUE 0x001
C_SKIP_7_VALUE 0x001
C_SKIP_SIM_INIT_DELAY
Perform Shorter Simulation Initialization
0
C_SPECIAL_BOARD
Xilinx Special Physical Layer for Spartan3x Boards
S3A_STKIT
C_SPLB0_AWIDTH 32
C_SPLB0_DWIDTH 64
C_SPLB0_MID_WIDTH 2
C_SPLB0_NATIVE_DWIDTH
Native Data Width of PLB
64
C_SPLB0_NUM_MASTERS 4
C_SPLB0_P2P 0
C_SPLB0_SMALLEST_MASTER 32
C_SPLB0_SUPPORT_BURSTS 1
C_SPLB1_AWIDTH 32
C_SPLB1_DWIDTH 64
C_SPLB1_MID_WIDTH 1
C_SPLB1_NATIVE_DWIDTH
Native Data Width of PLB
64
C_SPLB1_NUM_MASTERS 1
C_SPLB1_P2P 1
C_SPLB1_SMALLEST_MASTER 32
C_SPLB1_SUPPORT_BURSTS 0
C_SPLB2_AWIDTH 32
C_SPLB2_DWIDTH 64
C_SPLB2_MID_WIDTH 1
C_SPLB2_NATIVE_DWIDTH
Native Data Width of PLB
64
C_SPLB2_NUM_MASTERS 1
C_SPLB2_P2P 1
C_SPLB2_SMALLEST_MASTER 32
C_SPLB2_SUPPORT_BURSTS 0
C_SPLB3_AWIDTH 32
C_SPLB3_DWIDTH 64
C_SPLB3_MID_WIDTH 1
C_SPLB3_NATIVE_DWIDTH
Native Data Width of PLB
64
C_SPLB3_NUM_MASTERS 1
C_SPLB3_P2P 1
C_SPLB3_SMALLEST_MASTER 32
C_SPLB3_SUPPORT_BURSTS 0
C_SPLB4_AWIDTH 32
C_SPLB4_DWIDTH 64
C_SPLB4_MID_WIDTH 1
C_SPLB4_NATIVE_DWIDTH
Native Data Width of PLB
64
C_SPLB4_NUM_MASTERS 1
C_SPLB4_P2P 1
C_SPLB4_SMALLEST_MASTER 32
C_SPLB4_SUPPORT_BURSTS 0
C_SPLB5_AWIDTH 32
C_SPLB5_DWIDTH 64
C_SPLB5_MID_WIDTH 1
C_SPLB5_NATIVE_DWIDTH
Native Data Width of PLB
64
C_SPLB5_NUM_MASTERS 1
C_SPLB5_P2P 1
C_SPLB5_SMALLEST_MASTER 32
C_SPLB5_SUPPORT_BURSTS 0
C_SPLB6_AWIDTH 32
C_SPLB6_DWIDTH 64
C_SPLB6_MID_WIDTH 1
C_SPLB6_NATIVE_DWIDTH
Native Data Width of PLB
64
C_SPLB6_NUM_MASTERS 1
C_SPLB6_P2P 1
C_SPLB6_SMALLEST_MASTER 32
C_SPLB6_SUPPORT_BURSTS 0
C_SPLB7_AWIDTH 32
C_SPLB7_DWIDTH 64
C_SPLB7_MID_WIDTH 1
C_SPLB7_NATIVE_DWIDTH
Native Data Width of PLB
64
C_SPLB7_NUM_MASTERS 1
C_SPLB7_P2P 1
C_SPLB7_SMALLEST_MASTER 32
C_SPLB7_SUPPORT_BURSTS 0
C_STATIC_PHY_RDDATA_CLK_SEL
Sets Power-on/reset Value of RDDATA_CLK_SEL Register
0
C_STATIC_PHY_RDDATA_SWAP_RISE
Sets Power-on/reset Value of RDDATA_SWAP_RISE Register
0
C_STATIC_PHY_RDEN_DELAY
Sets Power-on/reset Value of RDENDELAY Register
5
C_TBY4TAPVALUE 9999
C_TWR 15000
C_USE_STATIC_PHY
Use Static PHY
0
C_VFBC0_CMD_AFULL_COUNT
VFBC Command FIFO Almost Full Count
3
C_VFBC0_CMD_FIFO_DEPTH
VFBC Command FIFO Depth
32
C_VFBC0_RDWD_DATA_WIDTH
VFBC Data FIFO Width
32
C_VFBC0_RDWD_FIFO_DEPTH
VFBC Data FIFO Depth
1024
C_VFBC0_RD_AEMPTY_WD_AFULL_COUNT
VFBC Data FIFO Almost Full/Empty Count
3
C_VFBC1_CMD_AFULL_COUNT
VFBC Command FIFO Almost Full Count
3
C_VFBC1_CMD_FIFO_DEPTH
VFBC Command FIFO Depth
32
C_VFBC1_RDWD_DATA_WIDTH
VFBC Data FIFO Width
32
C_VFBC1_RDWD_FIFO_DEPTH
VFBC Data FIFO Depth
1024
C_VFBC1_RD_AEMPTY_WD_AFULL_COUNT
VFBC Data FIFO Almost Full/Empty Count
3
C_VFBC2_CMD_AFULL_COUNT
VFBC Command FIFO Almost Full Count
3
C_VFBC2_CMD_FIFO_DEPTH
VFBC Command FIFO Depth
32
C_VFBC2_RDWD_DATA_WIDTH
VFBC Data FIFO Width
32
C_VFBC2_RDWD_FIFO_DEPTH
VFBC Data FIFO Depth
1024
C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT
VFBC Data FIFO Almost Full/Empty Count
3
C_VFBC3_CMD_AFULL_COUNT
VFBC Command FIFO Almost Full Count
3
C_VFBC3_CMD_FIFO_DEPTH
VFBC Command FIFO Depth
32
C_VFBC3_RDWD_DATA_WIDTH
VFBC Data FIFO Width
32
C_VFBC3_RDWD_FIFO_DEPTH
VFBC Data FIFO Depth
1024
C_VFBC3_RD_AEMPTY_WD_AFULL_COUNT
VFBC Data FIFO Almost Full/Empty Count
3
C_VFBC4_CMD_AFULL_COUNT
VFBC Command FIFO Almost Full Count
3
C_VFBC4_CMD_FIFO_DEPTH
VFBC Command FIFO Depth
32
C_VFBC4_RDWD_DATA_WIDTH
VFBC Data FIFO Width
32
C_VFBC4_RDWD_FIFO_DEPTH
VFBC Data FIFO Depth
1024
C_VFBC4_RD_AEMPTY_WD_AFULL_COUNT
VFBC Data FIFO Almost Full/Empty Count
3
C_VFBC5_CMD_AFULL_COUNT
VFBC Command FIFO Almost Full Count
3
C_VFBC5_CMD_FIFO_DEPTH
VFBC Command FIFO Depth
32
C_VFBC5_RDWD_DATA_WIDTH
VFBC Data FIFO Width
32
C_VFBC5_RDWD_FIFO_DEPTH
VFBC Data FIFO Depth
1024
C_VFBC5_RD_AEMPTY_WD_AFULL_COUNT
VFBC Data FIFO Almost Full/Empty Count
3
C_VFBC6_CMD_AFULL_COUNT
VFBC Command FIFO Almost Full Count
3
C_VFBC6_CMD_FIFO_DEPTH
VFBC Command FIFO Depth
32
C_VFBC6_RDWD_DATA_WIDTH
VFBC Data FIFO Width
32
C_VFBC6_RDWD_FIFO_DEPTH
VFBC Data FIFO Depth
1024
C_VFBC6_RD_AEMPTY_WD_AFULL_COUNT
VFBC Data FIFO Almost Full/Empty Count
3
C_VFBC7_CMD_AFULL_COUNT
VFBC Command FIFO Almost Full Count
3
C_VFBC7_CMD_FIFO_DEPTH
VFBC Command FIFO Depth
32
C_VFBC7_RDWD_DATA_WIDTH
VFBC Data FIFO Width
32
C_VFBC7_RDWD_FIFO_DEPTH
VFBC Data FIFO Depth
1024
C_VFBC7_RD_AEMPTY_WD_AFULL_COUNT
VFBC Data FIFO Almost Full/Empty Count
3
C_WR_DATAPATH_TML_PIPELINE
Write TML Pipeline
1
C_WR_TRAINING_PORT
Specifies Which Port's Write FIFO will be used for Memory Initialization
0
C_XCL0_LINESIZE
Cache Line Size
4
C_XCL0_PIPE_STAGES
XCL Pipe Stage
3
C_XCL0_WRITEXFER
Write Transfer
1
C_XCL1_LINESIZE
Cache Line Size
4
C_XCL1_PIPE_STAGES
XCL Pipe Stage
3
C_XCL1_WRITEXFER
Write Transfer
1
C_XCL2_LINESIZE
Cache Line Size
4
C_XCL2_PIPE_STAGES
XCL Pipe Stage
3
C_XCL2_WRITEXFER
Write Transfer
1
C_XCL3_LINESIZE
Cache Line Size
4
C_XCL3_PIPE_STAGES
XCL Pipe Stage
3
C_XCL3_WRITEXFER
Write Transfer
1
C_XCL4_LINESIZE
Cache Line Size
4
C_XCL4_PIPE_STAGES
XCL Pipe Stage
3
C_XCL4_WRITEXFER
Write Transfer
1
C_XCL5_LINESIZE
Cache Line Size
4
C_XCL5_PIPE_STAGES
XCL Pipe Stage
3
C_XCL5_WRITEXFER
Write Transfer
1
C_XCL6_LINESIZE
Cache Line Size
4
C_XCL6_PIPE_STAGES
XCL Pipe Stage
3
C_XCL6_WRITEXFER
Write Transfer
1
C_XCL7_LINESIZE
Cache Line Size
4
C_XCL7_PIPE_STAGES
XCL Pipe Stage
3
C_XCL7_WRITEXFER
Write Transfer
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1239 5888 21
Slice Flip Flops 1734 11776 14
4 input LUTs 1511 11776 12
IOs 10957 NA NA
bonded IOBs 47 372 12
BRAMs 5 20 25


dlmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus


dlmb_cntlr IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
INITIATOR BRAM_PORT XIL dlmb_port lmb_bram
SLAVE SLMB LMB dlmb microblaze_0


General
IP Core lmb_bram_if_cntlr
Version 2.10.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
LMB BRAM Base Address
0x00000000
C_HIGHADDR
LMB BRAM High Address
0x00001FFF
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_MASK
LMB Address Decode Mask
0x80000000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 5888 0
Slice Flip Flops 2 11776 0
4 input LUTs 6 11776 0
IOs 209 NA NA
bonded IOBs 0 372 0


ilmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus


ilmb_cntlr IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
INITIATOR BRAM_PORT XIL ilmb_port lmb_bram
SLAVE SLMB LMB ilmb microblaze_0


General
IP Core lmb_bram_if_cntlr
Version 2.10.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
LMB BRAM Base Address
0x00000000
C_HIGHADDR
LMB BRAM High Address
0x00001FFF
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_MASK
LMB Address Decode Mask
0x80000000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 5888 0
Slice Flip Flops 2 11776 0
4 input LUTs 6 11776 0
IOs 209 NA NA
bonded IOBs 0 372 0





Peripherals TOP
RS232_DCE   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.


RS232_DCE IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 RX I 1 fpga_0_RS232_DCE_RX
2 TX O 1 fpga_0_RS232_DCE_TX
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
SLAVE SPLB PLBV46 mb_plb xps_iic_0


General
IP Core xps_uartlite
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3a
C_BASEADDR
Base Address
0x84020000
C_HIGHADDR
High Address
0x8402FFFF
C_BAUDRATE
UART Lite Baud Rate
115200
C_DATA_BITS
Number of Data Bits in a Serial Frame
8
C_ODD_PARITY
Parity Type
0
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_CLK_FREQ_HZ
Clock Frequency of PLB Slave
66666667
 
Name Value
C_SPLB_DWIDTH
PLB Data Bus Width
64
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
2
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
4
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_USE_PARITY
Use Parity
0
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 114 5888 1
Slice Flip Flops 151 11776 1
4 input LUTs 136 11776 1
IOs 281 NA NA
bonded IOBs 0 372 0


RS232_DTE   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.


RS232_DTE IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 RX I 1 fpga_0_RS232_DTE_RX
2 TX O 1 fpga_0_RS232_DTE_TX
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
SLAVE SPLB PLBV46 mb_plb xps_iic_0


General
IP Core xps_uartlite
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3a
C_BASEADDR
Base Address
0x84000000
C_HIGHADDR
High Address
0x8400FFFF
C_BAUDRATE
UART Lite Baud Rate
115200
C_DATA_BITS
Number of Data Bits in a Serial Frame
8
C_ODD_PARITY
Parity Type
0
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_CLK_FREQ_HZ
Clock Frequency of PLB Slave
66666667
 
Name Value
C_SPLB_DWIDTH
PLB Data Bus Width
64
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
2
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
4
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_USE_PARITY
Use Parity
0
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 114 5888 1
Slice Flip Flops 151 11776 1
4 input LUTs 136 11776 1
IOs 281 NA NA
bonded IOBs 0 372 0


debug_module   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.


debug_module IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 Debug_SYS_Rst O 1 Debug_SYS_Rst
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
INITIATOR MBDEBUG_0 XIL microblaze_0_dbg microblaze_0
SLAVE SPLB PLBV46 mb_plb xps_iic_0


General
IP Core mdm
Version 1.00.d
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3a
C_BASEADDR
Base Address
0x84400000
C_HIGHADDR
High Address
0x8440FFFF
C_INTERCONNECT
Specifies the Bus Interface for the JTAG UART
1
C_JTAG_CHAIN
Specifies the JTAG user-defined register used
2
C_MB_DBG_PORTS
Number of MicroBlaze debug ports
1
C_OPB_AWIDTH
OPB Address Bus Width
32
C_OPB_DWIDTH
OPB Data Bus Width
32
C_SPLB_AWIDTH
PLB Address Bus Width
32
 
Name Value
C_SPLB_DWIDTH
PLB Data Bus Width
64
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
2
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
4
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
1
C_UART_WIDTH
UART Data size
8
C_USE_UART
Enable JTAG UART
1
C_WRITE_FSL_PORTS
Enable Write FSL Port
0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 90 5888 1
Slice Flip Flops 119 11776 1
4 input LUTs 132 11776 1
IOs 575 NA NA
bonded IOBs 0 372 0
GCLKs 2 24 8


proc_sys_reset_0   Processor System Reset Module
Reset management module


proc_sys_reset_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 Slowest_sync_clk I 1 sys_clk_s
2 Dcm_locked I 1 Dcm_all_locked
3 Ext_Reset_In I 1 sys_rst_s
4 MB_Debug_Sys_Rst I 1 Debug_SYS_Rst
5 MB_Reset O 1 mb_reset
6 Bus_Struct_Reset O 1 sys_bus_reset
7 Peripheral_Reset O 1 sys_periph_reset


General
IP Core proc_sys_reset
Version 2.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3a
C_AUX_RESET_HIGH
Auxiliary Reset Active High
1
C_AUX_RST_WIDTH
Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input
4
C_EXT_RESET_HIGH
External Reset Active High
1
C_EXT_RST_WIDTH
Number of Clocks Before Input Change is Recognized On The External Reset Input
4
C_NUM_BUS_RST
Number of Bus Structure Reset Registered Outputs
1
C_NUM_PERP_RST
Number of Peripheral Reset Registered Outputs
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 41 5888 0
Slice Flip Flops 67 11776 0
4 input LUTs 51 11776 0
IOs 20 NA NA
bonded IOBs 0 372 0


vdec1_plbv46_0   VDEC1_PLBV46



vdec1_plbv46_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
1 LLC_CLOCK I 1 video_in_rgb_0_LLC_CLOCK
2 YCrCb_in I 0:7 video_in_rgb_0_YCrCb_in
3 VDEC1_PWRDN_Z O 1 video_in_rgb_0_VDEC1_PWRDN_Z
4 VDEC1_OE_Z O 1 video_in_rgb_0_VDEC1_OE_Z
5 RESET_VDEC1_Z O 1 video_in_rgb_0_RESET_VDEC1_Z
6 led_debug O 0:7 xps_sdi_master_module_0_led_debug
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
MASTER MPLB PLBV46 mb_plb xps_iic_0
SLAVE SPLB PLBV46 mb_plb xps_iic_0


General
IP Core vdec1_plbv46
Version 1.00.a
Driver API
Parameters
These are parameters set for this module.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY spartan3a
C_BASEADDR 0xC2000000
C_HIGHADDR 0xC200FFFF
C_FAKE 4
C_INCLUDE_DPHASE_TIMER 0
C_MPLB_AWIDTH 32
C_MPLB_CLK_PERIOD_PS 10000
C_MPLB_DWIDTH 64
C_MPLB_NATIVE_DWIDTH 64
C_MPLB_P2P 0
 
Name Value
C_MPLB_SMALLEST_SLAVE 32
C_SPLB_AWIDTH 32
C_SPLB_CLK_PERIOD_PS 10000
C_SPLB_DWIDTH 64
C_SPLB_MID_WIDTH 2
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_NUM_MASTERS 4
C_SPLB_P2P 0
C_SPLB_SMALLEST_MASTER 32
C_SPLB_SUPPORT_BURSTS 0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1026 5888 17
Slice Flip Flops 991 11776 8
4 input LUTs 1858 11776 15
IOs 552 NA NA
bonded IOBs 0 372 0
BRAMs 8 20 40
MULT18X18SIOs 1 20 5
GCLKs 1 24 4


vga_16bit_plbv46_0   VGA_16BIT_PLBV46



vga_16bit_plbv46_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
1 clk_100m I 1 sys_clk50
2 blank_z O 1 vga_16bit_ML403_plbv46_0_blank_z
3 v_sync O 1 vga_16bit_ML403_plbv46_0_h_sync
4 h_sync O 1 vga_16bit_ML403_plbv46_0_v_sync
5 pixel_clk O 1 vga_16bit_ML403_plbv46_0_pixel_clk
6 blue O 0:3 vga_16bit_ML403_plbv46_0_blue
7 green O 0:3 vga_16bit_ML403_plbv46_0_green
8 red O 0:3 vga_16bit_ML403_plbv46_0_red
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
MASTER MPLB PLBV46 mb_plb xps_iic_0
SLAVE SPLB PLBV46 mb_plb xps_iic_0


General
IP Core vga_16bit_plbv46
Version 1.00.a
Driver API
Parameters
These are parameters set for this module.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY spartan3a
C_BASEADDR 0xCD600000
C_HIGHADDR 0xCD60FFFF
C_INCLUDE_DPHASE_TIMER 0
C_MPLB_AWIDTH 32
C_MPLB_CLK_PERIOD_PS 10000
C_MPLB_DWIDTH 64
C_MPLB_NATIVE_DWIDTH 64
C_MPLB_P2P 0
C_MPLB_SMALLEST_SLAVE 32
 
Name Value
C_SPLB_AWIDTH 32
C_SPLB_CLK_PERIOD_PS 10000
C_SPLB_DWIDTH 64
C_SPLB_MID_WIDTH 2
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_NUM_MASTERS 4
C_SPLB_P2P 0
C_SPLB_SMALLEST_MASTER 32
C_SPLB_SUPPORT_BURSTS 0
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 678 5888 11
Slice Flip Flops 772 11776 6
4 input LUTs 1907 11776 16
IOs 550 NA NA
bonded IOBs 0 372 0
GCLKs 1 24 4


xps_iic_0   XPS IIC Interface
PLBV46 interface to Philips I2C bus v2.1


xps_iic_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 Scl IO 1 xps_iic_0_Scl
2 Sda IO 1 xps_iic_0_Sda
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
SLAVE SPLB PLBV46 mb_plb vga_16bit_plbv46_0


General
IP Core xps_iic
Version 2.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3a
C_BASEADDR
Base Address
0x81600000
C_HIGHADDR
High Address
0x8160FFFF
C_CLK_FREQ
PLBv46 Bus Clock Frequency
25000000
C_GPO_WIDTH
Width of GPIO
1
C_IIC_FREQ
Output Frequency of SCL Signal
100000
C_SCL_INERTIAL_DELAY
Width of glitches removed on SCL input
0
 
Name Value
C_SDA_INERTIAL_DELAY
Width of glitches removed on SDA input
0
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
64
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
2
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
4
C_TEN_BIT_ADR
Use 10-bit Address
0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 305 5888 5
Slice Flip Flops 383 11776 3
4 input LUTs 460 11776 3
IOs 286 NA NA
bonded IOBs 0 372 0





IP TOP

clock_generator_0   Clock Generator
Clock generator for processor system.


clock_generator_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 CLKIN I 1 dcm_clk_s
2 RST I 1 net_gnd
3 CLKOUT0 O 1 sys_clk_s
4 CLKOUT1 O 1 DDR2_SDRAM_mpmc_clk_s
5 CLKOUT2 O 1 DDR2_SDRAM_mpmc_clk_90_s
6 LOCKED O 1 Dcm_all_locked
7 CLKOUT4 O 1 clk_100mhz


General
IP Core clock_generator
Version 2.01.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY spartan3a
C_CLKFBIN_BUF
Buffered:
FALSE
C_CLKFBIN_FREQ
Required frequency (Hz):
0
C_CLKFBOUT_BUF
Buffered:
TRUE
C_CLKFBOUT_FREQ
Frequency (Hz):
0
C_CLKFBOUT_MODULE NONE
C_CLKFBOUT_PORT NONE
C_CLKIN_BUF
Buffered:
FALSE
C_CLKIN_FREQ
Input clock frequency (Hz):
133333334
C_CLKOUT0_BUF
Buffered:
TRUE
C_CLKOUT0_FREQ
Required frequency (Hz):
66666667
C_CLKOUT0_GROUP
Grouping information:
NONE
C_CLKOUT0_MODULE NONE
C_CLKOUT0_PHASE
Required phase shift:
0
C_CLKOUT0_PORT NONE
C_CLKOUT10_BUF
Buffered:
TRUE
C_CLKOUT10_FREQ
Required frequency (Hz):
0
C_CLKOUT10_GROUP
Grouping information:
NONE
C_CLKOUT10_MODULE NONE
C_CLKOUT10_PHASE
Required phase shift:
0
C_CLKOUT10_PORT NONE
C_CLKOUT11_BUF
Buffered:
TRUE
C_CLKOUT11_FREQ
Required frequency (Hz):
0
C_CLKOUT11_GROUP
Grouping information:
NONE
C_CLKOUT11_MODULE NONE
C_CLKOUT11_PHASE
Required phase shift:
0
C_CLKOUT11_PORT NONE
C_CLKOUT12_BUF
Buffered:
TRUE
C_CLKOUT12_FREQ
Required frequency (Hz):
0
C_CLKOUT12_GROUP
Grouping information:
NONE
C_CLKOUT12_MODULE NONE
C_CLKOUT12_PHASE
Required phase shift:
0
C_CLKOUT12_PORT NONE
C_CLKOUT13_BUF
Buffered:
TRUE
C_CLKOUT13_FREQ
Required frequency (Hz):
0
C_CLKOUT13_GROUP
Grouping information:
NONE
C_CLKOUT13_MODULE NONE
C_CLKOUT13_PHASE
Required phase shift:
0
C_CLKOUT13_PORT NONE
C_CLKOUT14_BUF
Buffered:
TRUE
C_CLKOUT14_FREQ
Required frequency (Hz):
0
C_CLKOUT14_GROUP
Grouping information:
NONE
C_CLKOUT14_MODULE NONE
C_CLKOUT14_PHASE
Required phase shift:
0
C_CLKOUT14_PORT NONE
C_CLKOUT15_BUF
Buffered:
TRUE
C_CLKOUT15_FREQ
Required frequency (Hz):
0
C_CLKOUT15_GROUP
Grouping information:
NONE
C_CLKOUT15_MODULE NONE
C_CLKOUT15_PHASE
Required phase shift:
0
C_CLKOUT15_PORT NONE
C_CLKOUT1_BUF
Buffered:
TRUE
C_CLKOUT1_FREQ
Required frequency (Hz):
133333334
C_CLKOUT1_GROUP
Grouping information:
DCM0
C_CLKOUT1_MODULE NONE
C_CLKOUT1_PHASE
Required phase shift:
0
C_CLKOUT1_PORT NONE
C_CLKOUT2_BUF
Buffered:
TRUE
C_CLKOUT2_FREQ
Required frequency (Hz):
133333334
C_CLKOUT2_GROUP
Grouping information:
DCM0
C_CLKOUT2_MODULE NONE
C_CLKOUT2_PHASE
Required phase shift:
90
C_CLKOUT2_PORT NONE
C_CLKOUT3_BUF
Buffered:
TRUE
C_CLKOUT3_FREQ
Required frequency (Hz):
0
C_CLKOUT3_GROUP
Grouping information:
NONE
C_CLKOUT3_MODULE NONE
C_CLKOUT3_PHASE
Required phase shift:
0
C_CLKOUT3_PORT NONE
C_CLKOUT4_BUF
Buffered:
TRUE
C_CLKOUT4_FREQ
Required frequency (Hz):
50000000
C_CLKOUT4_GROUP
Grouping information:
NONE
C_CLKOUT4_MODULE NONE
C_CLKOUT4_PHASE
Required phase shift:
0
C_CLKOUT4_PORT NONE
C_CLKOUT5_BUF
Buffered:
TRUE
C_CLKOUT5_FREQ
Required frequency (Hz):
0
C_CLKOUT5_GROUP
Grouping information:
NONE
C_CLKOUT5_MODULE NONE
C_CLKOUT5_PHASE
Required phase shift:
0
C_CLKOUT5_PORT NONE
C_CLKOUT6_BUF
Buffered:
TRUE
C_CLKOUT6_FREQ
Required frequency (Hz):
0
C_CLKOUT6_GROUP
Grouping information:
NONE
C_CLKOUT6_MODULE NONE
C_CLKOUT6_PHASE
Required phase shift:
0
C_CLKOUT6_PORT NONE
C_CLKOUT7_BUF
Buffered:
TRUE
C_CLKOUT7_FREQ
Required frequency (Hz):
0
C_CLKOUT7_GROUP
Grouping information:
NONE
C_CLKOUT7_MODULE NONE
C_CLKOUT7_PHASE
Required phase shift:
0
C_CLKOUT7_PORT NONE
C_CLKOUT8_BUF
Buffered:
TRUE
C_CLKOUT8_FREQ
Required frequency (Hz):
0
C_CLKOUT8_GROUP
Grouping information:
NONE
C_CLKOUT8_MODULE NONE
C_CLKOUT8_PHASE
Required phase shift:
0
C_CLKOUT8_PORT NONE
C_CLKOUT9_BUF
Buffered:
TRUE
C_CLKOUT9_FREQ
Required frequency (Hz):
0
C_CLKOUT9_GROUP
Grouping information:
NONE
C_CLKOUT9_MODULE NONE
C_CLKOUT9_PHASE
Required phase shift:
0
C_CLKOUT9_PORT NONE
C_CLK_GEN 0
C_DCM0_CLK0_BUF false
C_DCM0_CLK180_BUF false
C_DCM0_CLK270_BUF false
C_DCM0_CLK2X180_BUF false
C_DCM0_CLK2X_BUF false
C_DCM0_CLK90_BUF false
C_DCM0_CLKDV180_BUF false
C_DCM0_CLKDV_BUF false
C_DCM0_CLKDV_DIVIDE 2.000000
C_DCM0_CLKFB_BUF false
C_DCM0_CLKFB_MODULE NONE
C_DCM0_CLKFB_PORT NONE
C_DCM0_CLKFX180_BUF false
C_DCM0_CLKFX_BUF false
C_DCM0_CLKFX_DIVIDE 1
C_DCM0_CLKFX_MULTIPLY 4
C_DCM0_CLKIN_BUF false
C_DCM0_CLKIN_DIVIDE_BY_2 false
C_DCM0_CLKIN_MODULE NONE
C_DCM0_CLKIN_PERIOD 0.000000
C_DCM0_CLKIN_PORT NONE
C_DCM0_CLKOUT_PHASE_SHIFT NONE
C_DCM0_CLK_FEEDBACK 1X
C_DCM0_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM0_DFS_FREQUENCY_MODE LOW
C_DCM0_DLL_FREQUENCY_MODE LOW
C_DCM0_DSS_MODE NONE
C_DCM0_DUTY_CYCLE_CORRECTION true
C_DCM0_EXT_RESET_HIGH 1
C_DCM0_FAMILY virtex5
C_DCM0_PHASE_SHIFT 0
C_DCM0_RST_MODULE NONE
C_DCM0_STARTUP_WAIT false
C_DCM1_CLK0_BUF false
C_DCM1_CLK180_BUF false
C_DCM1_CLK270_BUF false
C_DCM1_CLK2X180_BUF false
C_DCM1_CLK2X_BUF false
C_DCM1_CLK90_BUF false
C_DCM1_CLKDV180_BUF false
C_DCM1_CLKDV_BUF false
C_DCM1_CLKDV_DIVIDE 2.000000
C_DCM1_CLKFB_BUF false
C_DCM1_CLKFB_MODULE NONE
C_DCM1_CLKFB_PORT NONE
C_DCM1_CLKFX180_BUF false
C_DCM1_CLKFX_BUF false
C_DCM1_CLKFX_DIVIDE 1
C_DCM1_CLKFX_MULTIPLY 4
C_DCM1_CLKIN_BUF false
C_DCM1_CLKIN_DIVIDE_BY_2 false
C_DCM1_CLKIN_MODULE NONE
C_DCM1_CLKIN_PERIOD 0.000000
C_DCM1_CLKIN_PORT NONE
C_DCM1_CLKOUT_PHASE_SHIFT NONE
C_DCM1_CLK_FEEDBACK 1X
C_DCM1_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM1_DFS_FREQUENCY_MODE LOW
C_DCM1_DLL_FREQUENCY_MODE LOW
C_DCM1_DSS_MODE NONE
C_DCM1_DUTY_CYCLE_CORRECTION true
C_DCM1_EXT_RESET_HIGH 1
C_DCM1_FAMILY virtex5
C_DCM1_PHASE_SHIFT 0
 
Name Value
C_DCM1_RST_MODULE NONE
C_DCM1_STARTUP_WAIT false
C_DCM2_CLK0_BUF false
C_DCM2_CLK180_BUF false
C_DCM2_CLK270_BUF false
C_DCM2_CLK2X180_BUF false
C_DCM2_CLK2X_BUF false
C_DCM2_CLK90_BUF false
C_DCM2_CLKDV180_BUF false
C_DCM2_CLKDV_BUF false
C_DCM2_CLKDV_DIVIDE 2.000000
C_DCM2_CLKFB_BUF false
C_DCM2_CLKFB_MODULE NONE
C_DCM2_CLKFB_PORT NONE
C_DCM2_CLKFX180_BUF false
C_DCM2_CLKFX_BUF false
C_DCM2_CLKFX_DIVIDE 1
C_DCM2_CLKFX_MULTIPLY 4
C_DCM2_CLKIN_BUF false
C_DCM2_CLKIN_DIVIDE_BY_2 false
C_DCM2_CLKIN_MODULE NONE
C_DCM2_CLKIN_PERIOD 0.000000
C_DCM2_CLKIN_PORT NONE
C_DCM2_CLKOUT_PHASE_SHIFT NONE
C_DCM2_CLK_FEEDBACK 1X
C_DCM2_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM2_DFS_FREQUENCY_MODE LOW
C_DCM2_DLL_FREQUENCY_MODE LOW
C_DCM2_DSS_MODE NONE
C_DCM2_DUTY_CYCLE_CORRECTION true
C_DCM2_EXT_RESET_HIGH 1
C_DCM2_FAMILY virtex5
C_DCM2_PHASE_SHIFT 0
C_DCM2_RST_MODULE NONE
C_DCM2_STARTUP_WAIT false
C_DCM3_CLK0_BUF false
C_DCM3_CLK180_BUF false
C_DCM3_CLK270_BUF false
C_DCM3_CLK2X180_BUF false
C_DCM3_CLK2X_BUF false
C_DCM3_CLK90_BUF false
C_DCM3_CLKDV180_BUF false
C_DCM3_CLKDV_BUF false
C_DCM3_CLKDV_DIVIDE 2.000000
C_DCM3_CLKFB_BUF false
C_DCM3_CLKFB_MODULE NONE
C_DCM3_CLKFB_PORT NONE
C_DCM3_CLKFX180_BUF false
C_DCM3_CLKFX_BUF false
C_DCM3_CLKFX_DIVIDE 1
C_DCM3_CLKFX_MULTIPLY 4
C_DCM3_CLKIN_BUF false
C_DCM3_CLKIN_DIVIDE_BY_2 false
C_DCM3_CLKIN_MODULE NONE
C_DCM3_CLKIN_PERIOD 0.000000
C_DCM3_CLKIN_PORT NONE
C_DCM3_CLKOUT_PHASE_SHIFT NONE
C_DCM3_CLK_FEEDBACK 1X
C_DCM3_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM3_DFS_FREQUENCY_MODE LOW
C_DCM3_DLL_FREQUENCY_MODE LOW
C_DCM3_DSS_MODE NONE
C_DCM3_DUTY_CYCLE_CORRECTION true
C_DCM3_EXT_RESET_HIGH 1
C_DCM3_FAMILY virtex5
C_DCM3_PHASE_SHIFT 0
C_DCM3_RST_MODULE NONE
C_DCM3_STARTUP_WAIT false
C_EXT_RESET_HIGH 1
C_NUM_DCM 0
C_NUM_PLL 0
C_PLL0_BANDWIDTH OPTIMIZED
C_PLL0_CLKFBIN_MODULE NONE
C_PLL0_CLKFBIN_PORT NONE
C_PLL0_CLKFBOUT_BUF false
C_PLL0_CLKFBOUT_DESKEW_ADJUST PPC
C_PLL0_CLKFBOUT_MULT 1
C_PLL0_CLKFBOUT_PHASE 0.000000
C_PLL0_CLKIN1_BUF false
C_PLL0_CLKIN1_MODULE NONE
C_PLL0_CLKIN1_PERIOD 0.000000
C_PLL0_CLKIN1_PORT NONE
C_PLL0_CLKOUT0_BUF false
C_PLL0_CLKOUT0_DESKEW_ADJUST NONE
C_PLL0_CLKOUT0_DIVIDE 1
C_PLL0_CLKOUT0_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT0_PHASE 0.000000
C_PLL0_CLKOUT1_BUF false
C_PLL0_CLKOUT1_DESKEW_ADJUST NONE
C_PLL0_CLKOUT1_DIVIDE 1
C_PLL0_CLKOUT1_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT1_PHASE 0.000000
C_PLL0_CLKOUT2_BUF false
C_PLL0_CLKOUT2_DESKEW_ADJUST PPC
C_PLL0_CLKOUT2_DIVIDE 1
C_PLL0_CLKOUT2_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT2_PHASE 0.000000
C_PLL0_CLKOUT3_BUF false
C_PLL0_CLKOUT3_DESKEW_ADJUST PPC
C_PLL0_CLKOUT3_DIVIDE 1
C_PLL0_CLKOUT3_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT3_PHASE 0.000000
C_PLL0_CLKOUT4_BUF false
C_PLL0_CLKOUT4_DESKEW_ADJUST PPC
C_PLL0_CLKOUT4_DIVIDE 1
C_PLL0_CLKOUT4_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT4_PHASE 0.000000
C_PLL0_CLKOUT5_BUF false
C_PLL0_CLKOUT5_DESKEW_ADJUST PPC
C_PLL0_CLKOUT5_DIVIDE 1
C_PLL0_CLKOUT5_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT5_PHASE 0.000000
C_PLL0_COMPENSATION SYSTEM_SYNCHRONOUS
C_PLL0_DIVCLK_DIVIDE 1
C_PLL0_EXT_RESET_HIGH 1
C_PLL0_FAMILY virtex5
C_PLL0_REF_JITTER 0.100000
C_PLL0_RESET_ON_LOSS_OF_LOCK false
C_PLL0_RST_DEASSERT_CLK CLKIN1
C_PLL0_RST_MODULE NONE
C_PLL1_BANDWIDTH OPTIMIZED
C_PLL1_CLKFBIN_MODULE NONE
C_PLL1_CLKFBIN_PORT NONE
C_PLL1_CLKFBOUT_BUF false
C_PLL1_CLKFBOUT_DESKEW_ADJUST PPC
C_PLL1_CLKFBOUT_MULT 1
C_PLL1_CLKFBOUT_PHASE 0.000000
C_PLL1_CLKIN1_BUF false
C_PLL1_CLKIN1_MODULE NONE
C_PLL1_CLKIN1_PERIOD 0.000000
C_PLL1_CLKIN1_PORT NONE
C_PLL1_CLKOUT0_BUF false
C_PLL1_CLKOUT0_DESKEW_ADJUST NONE
C_PLL1_CLKOUT0_DIVIDE 1
C_PLL1_CLKOUT0_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT0_PHASE 0.000000
C_PLL1_CLKOUT1_BUF false
C_PLL1_CLKOUT1_DESKEW_ADJUST NONE
C_PLL1_CLKOUT1_DIVIDE 1
C_PLL1_CLKOUT1_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT1_PHASE 0.000000
C_PLL1_CLKOUT2_BUF false
C_PLL1_CLKOUT2_DESKEW_ADJUST PPC
C_PLL1_CLKOUT2_DIVIDE 1
C_PLL1_CLKOUT2_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT2_PHASE 0.000000
C_PLL1_CLKOUT3_BUF false
C_PLL1_CLKOUT3_DESKEW_ADJUST PPC
C_PLL1_CLKOUT3_DIVIDE 1
C_PLL1_CLKOUT3_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT3_PHASE 0.000000
C_PLL1_CLKOUT4_BUF false
C_PLL1_CLKOUT4_DESKEW_ADJUST PPC
C_PLL1_CLKOUT4_DIVIDE 1
C_PLL1_CLKOUT4_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT4_PHASE 0.000000
C_PLL1_CLKOUT5_BUF false
C_PLL1_CLKOUT5_DESKEW_ADJUST PPC
C_PLL1_CLKOUT5_DIVIDE 1
C_PLL1_CLKOUT5_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT5_PHASE 0.000000
C_PLL1_COMPENSATION SYSTEM_SYNCHRONOUS
C_PLL1_DIVCLK_DIVIDE 1
C_PLL1_EXT_RESET_HIGH 1
C_PLL1_FAMILY virtex5
C_PLL1_REF_JITTER 0.100000
C_PLL1_RESET_ON_LOSS_OF_LOCK false
C_PLL1_RST_DEASSERT_CLK CLKIN1
C_PLL1_RST_MODULE NONE
C_SPEEDGRADE -4
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 5888 0
Slice Flip Flops 5 11776 0
4 input LUTs 2 11776 0
IOs 21 NA NA
bonded IOBs 0 372 0
GCLKs 4 24 16
DCMs 1 8 12





Timing Information TOP


Post Synthesis Clock Limits
These are the post synthesis clock frequencies. The critical frequencies are marked with green.
The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system.
MODULE CLK Port MAX FREQ
vga_16bit_plbv46_0 SPLB_Clk 83.991MHz
vga_16bit_plbv46_0 MPLB_Clk 83.991MHz
vga_16bit_plbv46_0 vga_16bit_plbv46_0/clk_25m 83.991MHz
vga_16bit_plbv46_0 h_sync 83.991MHz
vga_16bit_plbv46_0 clk_100m 83.991MHz
vdec1_plbv46_0 SPLB_Clk 91.625MHz
vdec1_plbv46_0 LLC_CLOCK 91.625MHz
vdec1_plbv46_0 MPLB_Clk 91.625MHz
microblaze_0 DCACHE_FSL_OUT_CLK 98.415MHz
microblaze_0 DBG_CLK 98.415MHz
microblaze_0 DBG_UPDATE 98.415MHz
debug_module debug_module/update 101.133MHz
debug_module SPLB_Clk 101.133MHz
debug_module debug_module/drck_i 101.133MHz
xps_iic_0 SPLB_Clk 128.031MHz
mb_plb PLB_Clk 140.292MHz
RS232_DTE SPLB_Clk 146.864MHz
RS232_DCE SPLB_Clk 146.864MHz
proc_sys_reset_0 Slowest_sync_clk 207.555MHz
ilmb LMB_Clk 264.480MHz
dlmb LMB_Clk 264.480MHz
clock_generator_0 CLKIN 264.480MHz


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