Name |
Value |
C_PI4_PM_DC_CNTR
|
1 |
C_PI4_PM_USED
|
1 |
C_PI4_RD_FIFO_APP_PIPELINE
|
1 |
C_PI4_RD_FIFO_MEM_PIPELINE
|
1 |
C_PI4_RD_FIFO_TYPE |
BRAM |
C_PI4_WR_FIFO_APP_PIPELINE
|
1 |
C_PI4_WR_FIFO_MEM_PIPELINE
|
1 |
C_PI4_WR_FIFO_TYPE |
BRAM |
C_PI5_ADDRACK_PIPELINE
|
1 |
C_PI5_PM_DC_CNTR
|
1 |
C_PI5_PM_USED
|
1 |
C_PI5_RD_FIFO_APP_PIPELINE
|
1 |
C_PI5_RD_FIFO_MEM_PIPELINE
|
1 |
C_PI5_RD_FIFO_TYPE |
BRAM |
C_PI5_WR_FIFO_APP_PIPELINE
|
1 |
C_PI5_WR_FIFO_MEM_PIPELINE
|
1 |
C_PI5_WR_FIFO_TYPE |
BRAM |
C_PI6_ADDRACK_PIPELINE
|
1 |
C_PI6_PM_DC_CNTR
|
1 |
C_PI6_PM_USED
|
1 |
C_PI6_RD_FIFO_APP_PIPELINE
|
1 |
C_PI6_RD_FIFO_MEM_PIPELINE
|
1 |
C_PI6_RD_FIFO_TYPE |
BRAM |
C_PI6_WR_FIFO_APP_PIPELINE
|
1 |
C_PI6_WR_FIFO_MEM_PIPELINE
|
1 |
C_PI6_WR_FIFO_TYPE |
BRAM |
C_PI7_ADDRACK_PIPELINE
|
1 |
C_PI7_PM_DC_CNTR
|
1 |
C_PI7_PM_USED
|
1 |
C_PI7_RD_FIFO_APP_PIPELINE
|
1 |
C_PI7_RD_FIFO_MEM_PIPELINE
|
1 |
C_PI7_RD_FIFO_TYPE |
BRAM |
C_PI7_WR_FIFO_APP_PIPELINE
|
1 |
C_PI7_WR_FIFO_MEM_PIPELINE
|
1 |
C_PI7_WR_FIFO_TYPE |
BRAM |
C_PIM0_BASETYPE
|
2 |
C_PIM0_DATA_WIDTH NPI Width
|
64 |
C_PIM0_OFFSET
|
0x00000000 |
C_PIM0_SUBTYPE |
PLB |
C_PIM1_BASETYPE
|
0 |
C_PIM1_DATA_WIDTH NPI Width
|
64 |
C_PIM1_OFFSET
|
0x00000000 |
C_PIM1_SUBTYPE |
INACTIVE |
C_PIM2_BASETYPE
|
0 |
C_PIM2_DATA_WIDTH NPI Width
|
64 |
C_PIM2_OFFSET
|
0x00000000 |
C_PIM2_SUBTYPE |
INACTIVE |
C_PIM3_BASETYPE
|
0 |
C_PIM3_DATA_WIDTH NPI Width
|
64 |
C_PIM3_OFFSET
|
0x00000000 |
C_PIM3_SUBTYPE |
INACTIVE |
C_PIM4_BASETYPE
|
0 |
C_PIM4_DATA_WIDTH NPI Width
|
64 |
C_PIM4_OFFSET
|
0x00000000 |
C_PIM4_SUBTYPE |
INACTIVE |
C_PIM5_BASETYPE
|
0 |
C_PIM5_DATA_WIDTH NPI Width
|
64 |
C_PIM5_OFFSET
|
0x00000000 |
C_PIM5_SUBTYPE |
INACTIVE |
C_PIM6_BASETYPE
|
0 |
C_PIM6_DATA_WIDTH NPI Width
|
64 |
C_PIM6_OFFSET
|
0x00000000 |
C_PIM6_SUBTYPE |
INACTIVE |
C_PIM7_BASETYPE
|
0 |
C_PIM7_DATA_WIDTH NPI Width
|
64 |
C_PIM7_OFFSET
|
0x00000000 |
C_PIM7_SUBTYPE |
INACTIVE |
C_PM_DC_WIDTH <qt>Dead Cycle Counter Width</qt>
|
48 |
C_PM_ENABLE Enable Performance Monitor
|
0 |
C_PM_GC_CNTR <qt>Enable Global Cycle Counter</qt>
|
1 |
C_PM_GC_WIDTH <qt>Global Cycle Counter Width</qt>
|
48 |
C_PM_SHIFT_CNT_BY <qt>Shift Value of Trans Counter</qt>
|
1 |
C_PPC440MC0_BURST_LENGTH Burst Length
|
4 |
C_PPC440MC0_PIPE_STAGES Pipe Stage
|
1 |
C_PPC440MC1_BURST_LENGTH Burst Length
|
4 |
C_PPC440MC1_PIPE_STAGES Pipe Stage
|
1 |
C_PPC440MC2_BURST_LENGTH Burst Length
|
4 |
C_PPC440MC2_PIPE_STAGES Pipe Stage
|
1 |
C_PPC440MC3_BURST_LENGTH Burst Length
|
4 |
C_PPC440MC3_PIPE_STAGES Pipe Stage
|
1 |
C_PPC440MC4_BURST_LENGTH Burst Length
|
4 |
C_PPC440MC4_PIPE_STAGES Pipe Stage
|
1 |
C_PPC440MC5_BURST_LENGTH Burst Length
|
4 |
C_PPC440MC5_PIPE_STAGES Pipe Stage
|
1 |
C_PPC440MC6_BURST_LENGTH Burst Length
|
4 |
C_PPC440MC6_PIPE_STAGES Pipe Stage
|
1 |
C_PPC440MC7_BURST_LENGTH Burst Length
|
4 |
C_PPC440MC7_PIPE_STAGES Pipe Stage
|
1 |
C_RD_DATAPATH_TML_MAX_FANOUT Read Pipeline Max Fanout
|
0 |
C_SDMA0_COMPLETED_ERR_RX Enable Completed Err on RX
|
1 |
C_SDMA0_COMPLETED_ERR_TX Enable TX Completed Err
|
1 |
C_SDMA0_PI2LL_CLK_RATIO MPMC to SDMA Clk Ratio
|
1 |
C_SDMA0_PRESCALAR Clock Div. of Int. Timer Clk
|
1023 |
C_SDMA1_COMPLETED_ERR_RX Enable Completed Err on RX
|
1 |
C_SDMA1_COMPLETED_ERR_TX Enable Completed Err on TX
|
1 |
C_SDMA1_PI2LL_CLK_RATIO MPMC to SDMA Clk Ratio
|
1 |
C_SDMA1_PRESCALAR Clock Div. of Int. Timer Clk
|
1023 |
C_SDMA2_COMPLETED_ERR_RX Enable Completed Err on RX
|
1 |
C_SDMA2_COMPLETED_ERR_TX Enable Completed Err on TX
|
1 |
C_SDMA2_PI2LL_CLK_RATIO MPMC to SDMA Clk Ratio
|
1 |
C_SDMA2_PRESCALAR Clock Div. of Int. Timer Clk
|
1023 |
C_SDMA3_COMPLETED_ERR_RX Enable Completed Err on RX
|
1 |
C_SDMA3_COMPLETED_ERR_TX Enable Completed Err on TX
|
1 |
C_SDMA3_PI2LL_CLK_RATIO MPMC to SDMA Clk Ratio
|
1 |
C_SDMA3_PRESCALAR Clock Div. of Int. Timer Clk
|
1023 |
C_SDMA4_COMPLETED_ERR_RX Enable Completed Err on RX
|
1 |
C_SDMA4_COMPLETED_ERR_TX Enable Completed Err on TX
|
1 |
C_SDMA4_PI2LL_CLK_RATIO MPMC to SDMA Clk Ratio
|
1 |
C_SDMA4_PRESCALAR Clock Div. of Int. Timer Clk
|
1023 |
C_SDMA5_COMPLETED_ERR_RX Enable Completed Err on RX
|
1 |
C_SDMA5_COMPLETED_ERR_TX Enable Completed Err on TX
|
1 |
C_SDMA5_PI2LL_CLK_RATIO MPMC to SDMA Clk Ratio
|
1 |
C_SDMA5_PRESCALAR Clock Div. of Int. Timer Clk
|
1023 |
C_SDMA6_COMPLETED_ERR_RX Enable Completed Err on RX
|
1 |
C_SDMA6_COMPLETED_ERR_TX Enable Completed Err on TX
|
1 |
C_SDMA6_PI2LL_CLK_RATIO MPMC to SDMA Clk Ratio
|
1 |
C_SDMA6_PRESCALAR Clock Div. of Int. Timer Clk
|
1023 |
C_SDMA7_COMPLETED_ERR_RX Enable Completed Err on RX
|
1 |
C_SDMA7_COMPLETED_ERR_TX Enable Completed Err on TX
|
1 |
C_SDMA7_PI2LL_CLK_RATIO MPMC to SDMA Clk Ratio
|
1 |
C_SDMA7_PRESCALAR Clock Div. of Int. Timer Clk
|
1023 |
C_SDMA_CTRL0_AWIDTH |
32 |
C_SDMA_CTRL0_DWIDTH |
64 |
C_SDMA_CTRL0_MID_WIDTH |
1 |
C_SDMA_CTRL0_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL0_NUM_MASTERS |
1 |
C_SDMA_CTRL0_P2P |
1 |
C_SDMA_CTRL0_SMALLEST_MASTER |
32 |
C_SDMA_CTRL0_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL1_AWIDTH |
32 |
C_SDMA_CTRL1_DWIDTH |
64 |
C_SDMA_CTRL1_MID_WIDTH |
1 |
C_SDMA_CTRL1_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL1_NUM_MASTERS |
1 |
C_SDMA_CTRL1_P2P |
1 |
C_SDMA_CTRL1_SMALLEST_MASTER |
32 |
C_SDMA_CTRL1_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL2_AWIDTH |
32 |
C_SDMA_CTRL2_DWIDTH |
64 |
C_SDMA_CTRL2_MID_WIDTH |
1 |
C_SDMA_CTRL2_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL2_NUM_MASTERS |
1 |
C_SDMA_CTRL2_P2P |
1 |
C_SDMA_CTRL2_SMALLEST_MASTER |
32 |
C_SDMA_CTRL2_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL3_AWIDTH |
32 |
C_SDMA_CTRL3_DWIDTH |
64 |
C_SDMA_CTRL3_MID_WIDTH |
1 |
C_SDMA_CTRL3_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL3_NUM_MASTERS |
1 |
C_SDMA_CTRL3_P2P |
1 |
C_SDMA_CTRL3_SMALLEST_MASTER |
32 |
C_SDMA_CTRL3_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL4_AWIDTH |
32 |
C_SDMA_CTRL4_DWIDTH |
64 |
C_SDMA_CTRL4_MID_WIDTH |
1 |
C_SDMA_CTRL4_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL4_NUM_MASTERS |
1 |
C_SDMA_CTRL4_P2P |
1 |
C_SDMA_CTRL4_SMALLEST_MASTER |
32 |
C_SDMA_CTRL4_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL5_AWIDTH |
32 |
C_SDMA_CTRL5_DWIDTH |
64 |
C_SDMA_CTRL5_MID_WIDTH |
1 |
C_SDMA_CTRL5_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL5_NUM_MASTERS |
1 |
C_SDMA_CTRL5_P2P |
1 |
C_SDMA_CTRL5_SMALLEST_MASTER |
32 |
C_SDMA_CTRL5_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL6_AWIDTH |
32 |
C_SDMA_CTRL6_DWIDTH |
64 |
C_SDMA_CTRL6_MID_WIDTH |
1 |
C_SDMA_CTRL6_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL6_NUM_MASTERS |
1 |
C_SDMA_CTRL6_P2P |
1 |
C_SDMA_CTRL6_SMALLEST_MASTER |
32 |
C_SDMA_CTRL6_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL7_AWIDTH |
32 |
C_SDMA_CTRL7_DWIDTH |
64 |
C_SDMA_CTRL7_MID_WIDTH |
1 |
C_SDMA_CTRL7_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL7_NUM_MASTERS |
1 |
C_SDMA_CTRL7_P2P |
1 |
C_SDMA_CTRL7_SMALLEST_MASTER |
32 |
C_SDMA_CTRL7_SUPPORT_BURSTS |
0 |
C_SKIP_1_VALUE |
0x001 |
C_SKIP_2_VALUE |
0x001 |
C_SKIP_3_VALUE |
0x001 |
C_SKIP_4_VALUE |
0x001 |
C_SKIP_5_VALUE |
0x001 |
C_SKIP_6_VALUE |
0x001 |
C_SKIP_7_VALUE |
0x001 |
C_SKIP_SIM_INIT_DELAY Perform Shorter Simulation Initialization
|
0 |
C_SPECIAL_BOARD Xilinx Special Physical Layer for Spartan3x Boards
|
S3A_STKIT |
C_SPLB0_AWIDTH |
32 |
C_SPLB0_DWIDTH |
64 |
C_SPLB0_MID_WIDTH |
2 |
C_SPLB0_NATIVE_DWIDTH Native Data Width of PLB
|
64 |
C_SPLB0_NUM_MASTERS |
4 |
C_SPLB0_P2P |
0 |
C_SPLB0_SMALLEST_MASTER |
32 |
C_SPLB0_SUPPORT_BURSTS |
1 |
C_SPLB1_AWIDTH |
32 |
C_SPLB1_DWIDTH |
64 |
C_SPLB1_MID_WIDTH |
1 |
C_SPLB1_NATIVE_DWIDTH Native Data Width of PLB
|
64 |
C_SPLB1_NUM_MASTERS |
1 |
C_SPLB1_P2P |
1 |
C_SPLB1_SMALLEST_MASTER |
32 |
C_SPLB1_SUPPORT_BURSTS |
0 |
C_SPLB2_AWIDTH |
32 |
C_SPLB2_DWIDTH |
64 |
C_SPLB2_MID_WIDTH |
1 |
C_SPLB2_NATIVE_DWIDTH Native Data Width of PLB
|
64 |
C_SPLB2_NUM_MASTERS |
1 |
C_SPLB2_P2P |
1 |
C_SPLB2_SMALLEST_MASTER |
32 |
C_SPLB2_SUPPORT_BURSTS |
0 |
C_SPLB3_AWIDTH |
32 |
C_SPLB3_DWIDTH |
64 |
C_SPLB3_MID_WIDTH |
1 |
C_SPLB3_NATIVE_DWIDTH Native Data Width of PLB
|
64 |
C_SPLB3_NUM_MASTERS |
1 |
C_SPLB3_P2P |
1 |
C_SPLB3_SMALLEST_MASTER |
32 |
C_SPLB3_SUPPORT_BURSTS |
0 |
C_SPLB4_AWIDTH |
32 |
C_SPLB4_DWIDTH |
64 |
C_SPLB4_MID_WIDTH |
1 |
C_SPLB4_NATIVE_DWIDTH Native Data Width of PLB
|
64 |
C_SPLB4_NUM_MASTERS |
1 |
C_SPLB4_P2P |
1 |
C_SPLB4_SMALLEST_MASTER |
32 |
C_SPLB4_SUPPORT_BURSTS |
0 |
C_SPLB5_AWIDTH |
32 |
C_SPLB5_DWIDTH |
64 |
C_SPLB5_MID_WIDTH |
1 |
C_SPLB5_NATIVE_DWIDTH Native Data Width of PLB
|
64 |
C_SPLB5_NUM_MASTERS |
1 |
C_SPLB5_P2P |
1 |
C_SPLB5_SMALLEST_MASTER |
32 |
C_SPLB5_SUPPORT_BURSTS |
0 |
C_SPLB6_AWIDTH |
32 |
C_SPLB6_DWIDTH |
64 |
C_SPLB6_MID_WIDTH |
1 |
C_SPLB6_NATIVE_DWIDTH Native Data Width of PLB
|
64 |
C_SPLB6_NUM_MASTERS |
1 |
C_SPLB6_P2P |
1 |
C_SPLB6_SMALLEST_MASTER |
32 |
C_SPLB6_SUPPORT_BURSTS |
0 |
C_SPLB7_AWIDTH |
32 |
C_SPLB7_DWIDTH |
64 |
C_SPLB7_MID_WIDTH |
1 |
C_SPLB7_NATIVE_DWIDTH Native Data Width of PLB
|
64 |
C_SPLB7_NUM_MASTERS |
1 |
C_SPLB7_P2P |
1 |
C_SPLB7_SMALLEST_MASTER |
32 |
C_SPLB7_SUPPORT_BURSTS |
0 |
C_STATIC_PHY_RDDATA_CLK_SEL Sets Power-on/reset Value of RDDATA_CLK_SEL Register
|
0 |
C_STATIC_PHY_RDDATA_SWAP_RISE Sets Power-on/reset Value of RDDATA_SWAP_RISE Register
|
0 |
C_STATIC_PHY_RDEN_DELAY Sets Power-on/reset Value of RDENDELAY Register
|
5 |
C_TBY4TAPVALUE |
9999 |
C_TWR |
15000 |
C_USE_STATIC_PHY Use Static PHY
|
0 |
C_VFBC0_CMD_AFULL_COUNT VFBC Command FIFO Almost Full Count
|
3 |
C_VFBC0_CMD_FIFO_DEPTH VFBC Command FIFO Depth
|
32 |
C_VFBC0_RDWD_DATA_WIDTH VFBC Data FIFO Width
|
32 |
C_VFBC0_RDWD_FIFO_DEPTH VFBC Data FIFO Depth
|
1024 |
C_VFBC0_RD_AEMPTY_WD_AFULL_COUNT VFBC Data FIFO Almost Full/Empty Count
|
3 |
C_VFBC1_CMD_AFULL_COUNT VFBC Command FIFO Almost Full Count
|
3 |
C_VFBC1_CMD_FIFO_DEPTH VFBC Command FIFO Depth
|
32 |
C_VFBC1_RDWD_DATA_WIDTH VFBC Data FIFO Width
|
32 |
C_VFBC1_RDWD_FIFO_DEPTH VFBC Data FIFO Depth
|
1024 |
C_VFBC1_RD_AEMPTY_WD_AFULL_COUNT VFBC Data FIFO Almost Full/Empty Count
|
3 |
C_VFBC2_CMD_AFULL_COUNT VFBC Command FIFO Almost Full Count
|
3 |
C_VFBC2_CMD_FIFO_DEPTH VFBC Command FIFO Depth
|
32 |
C_VFBC2_RDWD_DATA_WIDTH VFBC Data FIFO Width
|
32 |
C_VFBC2_RDWD_FIFO_DEPTH VFBC Data FIFO Depth
|
1024 |
C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT VFBC Data FIFO Almost Full/Empty Count
|
3 |
C_VFBC3_CMD_AFULL_COUNT VFBC Command FIFO Almost Full Count
|
3 |
C_VFBC3_CMD_FIFO_DEPTH VFBC Command FIFO Depth
|
32 |
C_VFBC3_RDWD_DATA_WIDTH VFBC Data FIFO Width
|
32 |
C_VFBC3_RDWD_FIFO_DEPTH VFBC Data FIFO Depth
|
1024 |
C_VFBC3_RD_AEMPTY_WD_AFULL_COUNT VFBC Data FIFO Almost Full/Empty Count
|
3 |
C_VFBC4_CMD_AFULL_COUNT VFBC Command FIFO Almost Full Count
|
3 |
C_VFBC4_CMD_FIFO_DEPTH VFBC Command FIFO Depth
|
32 |
C_VFBC4_RDWD_DATA_WIDTH VFBC Data FIFO Width
|
32 |
C_VFBC4_RDWD_FIFO_DEPTH VFBC Data FIFO Depth
|
1024 |
C_VFBC4_RD_AEMPTY_WD_AFULL_COUNT VFBC Data FIFO Almost Full/Empty Count
|
3 |
C_VFBC5_CMD_AFULL_COUNT VFBC Command FIFO Almost Full Count
|
3 |
C_VFBC5_CMD_FIFO_DEPTH VFBC Command FIFO Depth
|
32 |
C_VFBC5_RDWD_DATA_WIDTH VFBC Data FIFO Width
|
32 |
C_VFBC5_RDWD_FIFO_DEPTH VFBC Data FIFO Depth
|
1024 |
C_VFBC5_RD_AEMPTY_WD_AFULL_COUNT VFBC Data FIFO Almost Full/Empty Count
|
3 |
C_VFBC6_CMD_AFULL_COUNT VFBC Command FIFO Almost Full Count
|
3 |
C_VFBC6_CMD_FIFO_DEPTH VFBC Command FIFO Depth
|
32 |
C_VFBC6_RDWD_DATA_WIDTH VFBC Data FIFO Width
|
32 |
C_VFBC6_RDWD_FIFO_DEPTH VFBC Data FIFO Depth
|
1024 |
C_VFBC6_RD_AEMPTY_WD_AFULL_COUNT VFBC Data FIFO Almost Full/Empty Count
|
3 |
C_VFBC7_CMD_AFULL_COUNT VFBC Command FIFO Almost Full Count
|
3 |
C_VFBC7_CMD_FIFO_DEPTH VFBC Command FIFO Depth
|
32 |
C_VFBC7_RDWD_DATA_WIDTH VFBC Data FIFO Width
|
32 |
C_VFBC7_RDWD_FIFO_DEPTH VFBC Data FIFO Depth
|
1024 |
C_VFBC7_RD_AEMPTY_WD_AFULL_COUNT VFBC Data FIFO Almost Full/Empty Count
|
3 |
C_WR_DATAPATH_TML_PIPELINE Write TML Pipeline
|
1 |
C_WR_TRAINING_PORT Specifies Which Port's Write FIFO will be used for Memory Initialization
|
0 |
C_XCL0_LINESIZE Cache Line Size
|
4 |
C_XCL0_PIPE_STAGES XCL Pipe Stage
|
3 |
C_XCL0_WRITEXFER Write Transfer
|
1 |
C_XCL1_LINESIZE Cache Line Size
|
4 |
C_XCL1_PIPE_STAGES XCL Pipe Stage
|
3 |
C_XCL1_WRITEXFER Write Transfer
|
1 |
C_XCL2_LINESIZE Cache Line Size
|
4 |
C_XCL2_PIPE_STAGES XCL Pipe Stage
|
3 |
C_XCL2_WRITEXFER Write Transfer
|
1 |
C_XCL3_LINESIZE Cache Line Size
|
4 |
C_XCL3_PIPE_STAGES XCL Pipe Stage
|
3 |
C_XCL3_WRITEXFER Write Transfer
|
1 |
C_XCL4_LINESIZE Cache Line Size
|
4 |
C_XCL4_PIPE_STAGES XCL Pipe Stage
|
3 |
C_XCL4_WRITEXFER Write Transfer
|
1 |
C_XCL5_LINESIZE Cache Line Size
|
4 |
C_XCL5_PIPE_STAGES XCL Pipe Stage
|
3 |
C_XCL5_WRITEXFER Write Transfer
|
1 |
C_XCL6_LINESIZE Cache Line Size
|
4 |
C_XCL6_PIPE_STAGES XCL Pipe Stage
|
3 |
C_XCL6_WRITEXFER Write Transfer
|
1 |
C_XCL7_LINESIZE Cache Line Size
|
4 |
C_XCL7_PIPE_STAGES XCL Pipe Stage
|
3 |
C_XCL7_WRITEXFER Write Transfer
|
1 |