BlockDiagram

EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
0A fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin I 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I
1A fpga_0_DDR2_SDRAM_DDR2_DQ IO 15:0 fpga_0_DDR2_SDRAM_DDR2_DQ
2A fpga_0_DDR2_SDRAM_DDR2_DQS IO 1:0 fpga_0_DDR2_SDRAM_DDR2_DQS
3A fpga_0_DDR2_SDRAM_DDR2_DQS_n IO 1:0 fpga_0_DDR2_SDRAM_DDR2_DQS_n
4A fpga_0_DDR2_SDRAM_DDR2_Addr_pin O 12:0 fpga_0_DDR2_SDRAM_DDR2_Addr
5A fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_BankAddr
6A fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CAS_n
7A fpga_0_DDR2_SDRAM_DDR2_CE_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CE
8A fpga_0_DDR2_SDRAM_DDR2_CS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CS_n
9A fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_Clk_n
10A fpga_0_DDR2_SDRAM_DDR2_Clk_pin O 1 fpga_0_DDR2_SDRAM_DDR2_Clk
11A fpga_0_DDR2_SDRAM_DDR2_DM_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_DM
12A fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin O 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O
13A fpga_0_DDR2_SDRAM_DDR2_ODT_pin O 1 fpga_0_DDR2_SDRAM_DDR2_ODT
14A fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_RAS_n
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
15A fpga_0_DDR2_SDRAM_DDR2_WE_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_WE_n
16B fpga_0_RS232_DCE_RX_pin I 1 fpga_0_RS232_DCE_RX
17B fpga_0_RS232_DCE_TX_pin O 1 fpga_0_RS232_DCE_TX
18C fpga_0_RS232_DTE_RX_pin I 1 fpga_0_RS232_DTE_RX
19C fpga_0_RS232_DTE_TX_pin O 1 fpga_0_RS232_DTE_TX
20D sys_clk_pin I 1 dcm_clk_s  CLK 
21E sys_rst_pin I 1 sys_rst_s  RESET 
22F sys_clk50_pin I 1 sys_clk50  CLK 
23F vga_16bit_ML403_plbv46_0_blank_z_pin O 1 vga_16bit_ML403_plbv46_0_blank_z
24F vga_16bit_ML403_plbv46_0_blue_pin O 3:0 vga_16bit_ML403_plbv46_0_blue
25F vga_16bit_ML403_plbv46_0_green_pin O 3:0 vga_16bit_ML403_plbv46_0_green
26F vga_16bit_ML403_plbv46_0_h_sync_pin O 1 vga_16bit_ML403_plbv46_0_h_sync
27F vga_16bit_ML403_plbv46_0_pixel_clk_pin O 1 vga_16bit_ML403_plbv46_0_pixel_clk
28F vga_16bit_ML403_plbv46_0_red_pin O 3:0 vga_16bit_ML403_plbv46_0_red
29F vga_16bit_ML403_plbv46_0_v_sync_pin O 1 vga_16bit_ML403_plbv46_0_v_sync