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Dynamic Partial Reconfiguration and Self-Organization

FPGA technologies offer huge advantages in PICSy Project. In particulars, dynamic partial reconfiguration allows to modify the SoC at run-time. New hardware modules are by consequence exchangeable on a network.

Figure 1 shows an example of such Dynamic Partial Reconfigurable SoC (DPR-SoC). Modules can be store in a local memory or somewhere in a network under the form of a files named bitstream.

Dynamic Partial Reconfiguration techniques are used to modify the SoC architecture at run-time. This allows the addition of new hardware modules without service interruptions. Such complexe system requires to divide the SoC into a static and a dynamic regions. Dynamically reconfigurable regions are separated from the static region by fix interfaces called bus macro. All control and data signals must pass through them. Reconfigurable Modules are stored in a external memory in the form of a file called bitstream. Thanks to a Linux operating system, bitstreams files can be managed and exchanged on a network.