2022
-
G. Duchrau, M. Gössel
"A New Decoding Method for Double Error Correcting Cross Parity Codes."
28th International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE,
2022
-
C. Schulz-Hanke
"Vereinfachung der Bestimmung von 4-Bit Fehlern für BCH Codes"
34. Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2022,
Februar 2022
2021
-
G. Duchrau, M. Gössel
"Kürzen von BCH-Codes zur Reduzierung der Anzahl der Prüfbits"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2021,
S.65-67,
Februar 2021
2019
-
P.-P. Nordmann, M. Gössel
"A new DEC/TED code for fast correction of 2-bit-errors" (accepted)
25th IEEE International Symposium on On-Line Testing and Robust System Design - IOLTS 2019,
Juli 2019,
Rhodos, Greece
-
P.-P. Nordmann, M. Gössel
"Regular LPDC Codes with guaranteed Hamming distance and low density G-Matrix"
BELAS Biannual European - Latin American Summer School on Design, Test and Reliability,
June 2019,
Frankfurt (Oder), Germany
-
P.-P. Nordmann
"Recursive Generation of a new LDPC-Code"
Workshop Technologies for Efficient Fault Management towards Error-Resilient Electronic Systems,
März 2019,
Cottbus, Germany
-
C. Schulz-Hanke
"Fast multi-bit fault detection for BCH-Code"
Workshop Technologies for Efficient Fault Management towards Error-Resilient Electronic Systems,
März 2019,
Cottbus, Germany
-
A. Klockmann, M. Gössel
"Modified multi-valued Berger codes"
Workshop Technologies for Efficient Fault Management towards Error-Resilient Electronic Systems,
März 2019,
Cottbus, Germany
-
P.-P. Nordmann, M. Gössel
"Modifizierter DEC/TED BCH-Code zur schnellen Decodierung"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2019,
S. 17-18,
Februar 2019,
Prien am Chiemsee, Germany.
2018
-
A. Klockmann, M. Gössel
"Generalized Non-Binary Berger Codes"
Sixteenth International Workshop on Algebraic and Combinatorial Coding Theory - ACCT XVI,
September 2018,
Svetlogorsk, Russia
-
P.-P. Nordmann, M. Gössel
"Regular LPDC Codes with guaranteed Hamming distance and low density G-Matrix"
Munich Workshop on Coding and Cryptography - MWCC 2018,
April 2018,
München, Germany
-
A. Klockmann, G. Georgakos, M. Gössel
"A New 3-Bit Burst-Error Correcting Code"
Munich Workshop on Coding and Cryptography - MWCC 2018,
April 2018,
München, Germany
(as presented at IOLTS 2017)
-
P.-P.Nordmann, M. Gössel
"Regular LPDC Codes with Guaranteed Minimal Hamming Distance"
Journal of Automata, Languages and Combinatorics: Volume 23, Numbers 1-3,
S. 271-280,
2018
2017
-
A. Klockmann, G. Georgakos, M. Gössel
"Systematic Design of a New 3-Bit-Burst-Error Correction Code with Minimal Number of Check Bits"
Zuverlässigkeit und Entwurf - ZuE 2017,
September 2017,
Cottbus, Germany
-
A. Klockmann, G. Georgakos, M. Gössel
"A New 3-Bit Burst-Error Correcting Code"
23rd IEEE International Symposium on On-Line Testing and Robust System Design - IOLTS 2017,
Juli 2017,
Thessaloniki, Greece
-
S. Weidling, M. Krstić, M. Gössel
"Identifizierung fehlerbewahrender Speicherelemente zur Vermeidung der Fehlerakkumulation"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2017,
S. 55-58,
März 2017,
Lübeck, Germany.
2016
-
G. Niess, Th. Kern, M. Gössel
"Determination of Almost Optimal Check Bits"
Chapter 3.4 in "Problems and New Solutions in the Boolean Domain",
ed. Steinbach, B.,
Cambridge Scholars Publishing, Newcastle, UK,
2016
-
S. Weidling, M. Krstić, V. Petrović, E.S. Sogomonyan
"Architektur mit reduzierter Komplexität zur Erkennung und Korrektur von transienten Fehlern in
kombinatorischer und sequentieller Logik"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2016,
März 2016,
Siegen, Germany.
-
M. Krstić, S. Weidling, V. Petrović, E. S. Sogomonyan
"Enhanced Architectures for Soft Error Detection and Correction in Combinational and Sequential Circuits"
Microelectronics Reliability, Volume 56,
January 2016,
Pages 212-220,
Elsevier, Amsterdam, Netherlands.
2015
- M. Krstić, G. Schoof, V. Petrović, S. Weidling, E.S. Sogomonyan, M. Gössel
"Schaltungsanordnung mit Detektion oder Behandlung von transienten Fehlern in einem kombinatorischen Schaltungsteil"
Patent, Nr.: DE 102013225039, 11. Juni 2015
- G. Nieß, T. Kern, M. Gössel
"Möglichkeiten der Modellierung von Fehlern in MLC-Flash-Speichern durch Fehlergraphen"
45. Jahrestagung der Gesellschaft für Informatik, INFORMATIK 2015, S. 1445 - 1460, Cottbus, Germany.
- G. Nieß, T. Kern, M. Gössel
"Error Detection Codes for Arbitrary Errors Modeled by Error Graphs"
11th Workshop on Dependability and Fault Tolerance - VERFE 2015, March 2015, Porto, Portugal.
- S. Weidling, M. Krstić, V. Petrović, M. Gössel
"Neue Methodik zur Implementierung fehlertoleranter pipeline-basierter Architekturen"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2015, S. 86 - 89, März 2015, Bad Urach, Germany.
2014
- M. Gössel, M. Richter, T. Rabenalt
"High Performance Compaction for Test Responses with many Unknowns"
US Patent, No.: US 8,898,529, Nov. 25, 2014
- M. Augustin, M. Gössel, R. Krämer
"Electronic Circuit Arrangement for Processing Binary Input Values"
US Patent, No.: US 8,884,643, Nov. 11, 2014
- G. Nieß, T. Kern, M. Gössel
"Determination of Almost Optimal Check Bits for an Arbitrary Error Model"
11th International Workshop on Boolean Problems, September 2014, Freiberg, Germany.
- M. Krstic, S. Weidling, V. Petrovic, M. Gössel
"Improved Circuitry for Soft Error Correction in Combinational Logic in Pipelined Designs"
20th IEEE International On-Line Testing Symposium, July 2014, Platja d'Aro, Spain.
- Ch. Badack, T. Kern, M. Gössel
"Modified DEC BCH Codes for Parallel Correction of 3-bit Errors Comprising a Pair of Adjacent Errors"
20th IEEE International On-Line Testing Symposium, July 2014, Platja d'Aro, Spain.
- Ch. Badack, M. Gössel
"Triple Error Detection for Imai-Kamiyanagi Codes Based on Subsyndrome Computations"
19th IEEE European Test Symposium, May 2014, Paderborn, Germany.
- Ch. Badack, M. Gössel
"Error Detection for Imai-Kamiyanagi Codes"
3rd Biannual European - Latin American Summer School on Design, Test and Reliability, April 2014, Frankfurt (Oder), Germany.
- S. Weidling, M. Gössel
"Fault Tolerant Linear State Machines"
Proc. 15th IEEE Latin-American Test Workshop, March 2014, Fortaleza, Brazil.
- S. Hosp, M. Gössel
"Modifizierung des Cross-Parity-Codes"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2014, S. 45 - 48, Kloster Banz, Germany.
2013
- S. Weidling, E. Sogomonyan, M. Gössel
"Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection"
Proc. 16th Euromicro Conference on Digital System Design, September 2013, pp. 855-862.
- T. Kern, U. Backhausen, M. Gössel, T. Rabenalt, S. Lacouture
"Apparatus and method for correcting at least one bit error within a coded bit sequence"
US Patent, No.: US 8,539,321 B2, Sep. 17, 2013
- U. Backhausen, M. Gössel, T. Kern, T. Rabenalt
"Method and apparatus for storing data"
US Patent, No.: US 8,533,566 B2, Sep. 10, 2013
- E. Sogomonyan, S. Weidling, M. Gössel
"A new method for correcting time and soft errors in combinational circuits"
Proc. 16th DDECs, 2013, pp. 283-286.
- S. Deutsch, S. Hosp, G. Nieß, K. Chakrabarty
"Heuristik zur Lokalisierung defekter TSVs"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2013, Dresden, S. 75 - 78.
2012
- E. Sogomonyan, D. Marienfeld, M. Gössel
"Circuit Arrangement"
US Patent, No.: US 8,219,864 B2, July 10, 2012
- T. Rabenalt, M. Richter, F. Poehl, M. Gössel
"Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique"
Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Issue 6, P. 950 - 957, June 2012.
- E. Sogomonyan, M. Gössel
"Circuit Arrangement and Method for Error Detection and Arrangement for Monitoring of a Digital Circuit"
US Patent, No.: US 8,136,009 B2, March 13, 2012
- G. Nieß, E. Sogomonyan, M. Gössel, T. Kern und T. Rabenalt
"Innere Codes mit nichtlinearen Split-Parity Prüfbits"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2012, Cottbus, S. 35 - 40.
- M. Augustin, M. Goessel, G. Schoof und R. Kraemer
"Entwurf fehlertoleranter Zustandsautomaten mit variablem Schutz für spezifische Eingabesequenzen"
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2012, Cottbus, S. 47 - 52.
- M. Richter und K. Chakrabarty
"Test Pin Count Reduction for NoC-based Test Delivery in Multicore SOCs"
Design, Automation and Test in Europe Conference - DATE, IEEE Press, Dresden, Germany, 2012.
2011
- M. Augustin, M. Goessel und R. Kraemer
"Effiziente Synthese von Schaltungen mit spezifischer Fehlertoleranz"
Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen, 2011, S. 93-98.
- M. Augustin, M. Goessel und R. Kraemer
"Implementation of Selective Fault-Tolerance with Conventional Synthesis Tools"
Proc. 14th DDECs, 2011, pp. 213-218.
- T. Rabenalt, M. Gössel, A. Leininger
"Masking X-values by Use of a Hierarchically Configurable Register",
Jornal of Electronic Testing: Volume 27, Issue 1, S. 31 - 41, 2011
2010
- T. Rabenalt, M. Richter und M. Goessel
"High Performance Compaction for Test Responses with many Unknowns"
Proc. 19th Asian Test Symposium, Shanghai, 2010
- M. Augustin, M. Goessel, R. Kraemer
"Eine neue Fehlertoleranzmethode zur Verringerung des Flächenaufwands von TMR-Systemen"
Proc. Zuverlässigkeit und Entwurf, S. 98-96, 4. GMM/GI/ITG-Fachtagung, Wildbad-Kreuth 2010
- Hilscher, M., Seuting, M., Leininger,L. und M. Goessel
"Hierarchischer Kompaktor: effiziente Testdatenkompaktierung mit X-Werten an modernen Testern"
Proc. TuZ 2010, S. 45-50, Paderborn 2010
- Augustin, M, Goessel,M. and R. Kraemer
Reducing the Area Overhead of TMR-Systems by Protecting Specific Signals
Proc. IOLTS, pp. 268-273, Corfu, 2010
2009
- M. Richter, M. Gössel
"Concurrent Error Detection with Split-Parity Codes"
Proc. 15th IEEE International On-Line Testing Symposium, S. 159-163, Portugal, June 2009
- M. Hilscher, M. Braun, M. Richter, A. Leininger, M. Gössel
"X-tolerant Test Data Compaction with Accelerated Shift Registers"
Journal of Electronic Testing, Theory and Applications (JETTA) Vol 25, S. 247-258, 2009
- T. Rabenalt, M. Gössel, A. Leininger
"Masking X-values by Use of a Hierarchically Configurable Register",
Conference Proceedings ETS 2009, ISBN 978-0-7695-3703-0, S. 149-154, Sevilla, Spain, 2009
- F.-U. Faber, M. Beck, M. Rudack, O. Barondeau, T. Rabenalt, M. Gössel, A. Leininger
"Doubling Test Cell Throughput by On-Loadbord Hardware - Implementation and Experience in a Production Environment",
Conference Proceedings ETS 2009, ISBN 978-0-7695-3703-0, S. 39-44, Sevilla, Spain, 2009
- F. Börner, A. Leininger, M. Gössel
"Convolutional Compactors for Guaranteed 6-Bit Error Detection",
Algorithms, Architectures and Information Systems Security, Editors: Bhattacharya, Sur-Kolay, Nandy, Bagchi,
S. 97-115, World Scientific,ISBN-10 981-283-623-3, 2009
- T. Rabenalt, M. Hilscher, A. Leininger, M. Gössel
"Hierarchisch konfigurierbares Register zur Maskierung von X-Werten",
ITG/GI/GMM 21. Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen,
S. 21-26, Bremen, 2009
2008
- M. Richter, K. Oberländer, M. Gössel
"New linear SEC-DED codes with reduced triple bit miscorrection probability"
Proc. 14th International On-Line Testing Symposium, Rhodes, Greece, July 2008
- M. Hilscher, M. Braun, M. Richter, A. Leininger, M. Gössel
"Accelerated Shift Registers for X-tolerant Test Data Compaction",
Conference Proceedings ETS 2008, ISBN 978-0-7695-3150-2, S. 133-139, Verbania, 2008
- M. Hilscher, M. Richter, A. Leininger, M. Gössel
"Gruppen von beschleunigten Schieberegistern zur X-toleranten Testdatenkompaktierung",
ITG/GI/GMM 20. Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen,
S. 109-113, Wien, 2008
- T. Rabenalt, J. Rzeha, A. Leininger, M. Rudack, M. Gössel
"Effiziente On-Chip Speicherung von Scan-Diagnosedaten",
ITG/GI/GMM 20. Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen,
S. 1-5, Wien, 2008
- M. Gössel, E. Sogomonyan
"A Non-linear Split Error Detection Code",
Fundamenta Informaticae, Bd. 83 (1-2), 109-115, 2008.
2007
- A. Leininger, M. Richter, M. Braun, M. Fischer, M. Gössel
"Using Timing Flexibility of Automatic Test Equipment to Complement X-tolerant Test Compression Techniques",
Conference Proceedings ITC 2007, paper 6.3, Santa Clara, 2007
- F. Poehl, M. Beck, R. Arnold, J. Rzeha, T. Rabenalt, M. Gössel:
"On-chip evaluation, compensation, and storage of scan diagnosis data",
IET Computer & Digital Techniques,Volume 1, Issue 3, ISSN 1751-8601, S. 207-212, 2007
- E. S. Sogomonyan, D. Marienfeld, M. Gössel:
"Fehlererkennung mit Fehlerkorrektur für Soft Errors",
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, S. 185-188, München, 2007
- M. Richter, A.Leininger, M. Gössel:
"Schnelle Kompaktierung von Testdaten mit X-Werten durch MISR ohne Rückkopplung",
ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, S. 7-11, Erlangen, 2007
- M. Gössel:
"Neue Methoden der Online-Fehlererkennung",
ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Erlangen, 2007
2006
- D. Marienfeld, E.S. Sogomonyan, V. Otcheretnij, M.Goessel:
"A New Self-Checking and Code-Disjoint Non-Restoring Array Divider",
Proc. 12th IEEE On-Line Testing Symposium,pp. 23-28, Como, Italy, July 2006
- F. Poehl, J. Rzeha, M. Beck, M. Goessel, R. Arnold, P. Ossimitz:
"On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture",
11th IEEE European Test Symposium, Formal Proceedings, pp. 239-246, Southampton, England, May 2006.
- Otcheretnij,V., Goessel,M., Sogomonyan,E. and Marienfeld,D.:
"Modulo p=3 Checking for a Carry Select Adder",
Journal of Electronic Testing, Theory and Applications (JETTA) Vol 22, pp 101- 107, 2006.
- Wang,Z. Chakrabarty,K. and Goessel,M.:
"Test Set Enrichment using a Probabilistic Faul Model and the Theory of Output Deviations",
Proc. DATE 2006, pp. 1270-1276.
- J. Rzeha, M. Beck, F. Poehl, and M. Gössel :
"Kompaktor Architektur zur Reduktion und Kompensation von Test- und Diagnosedaten On-Chip",
ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, S. 49-52, 2006.
2005
- D. Marienfeld, E. S. Sogomonyan, V. Otscheretnij and M.Goessel:
"New Self-Checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors",
14th Asian Test Symposium, pp. 76-81, Calcutta, India, Dezember 2005
- V. Otscheretnij, G. Kouznetzov, R.Karri and M.Goessel:
"On-Line Error Detection and BIST for the AES Encryption Algorythm with Different S-Box Implementations",
11th IEEE International On-Line Testing Symposium, pp. 141-146, St. Raphael, France, Juli 2005.
2004
- K. Wu, R.Karri, G. Kouznetzov and M.Goessel:
"Low Cost Concurrent Error Detection for the Advanced Encryption Standard",
Proc. ITC 2004, pp. 1242-1248, 2004.
- M. Goessel, K. Chakrabarty, V. Otscheretnij and A. Leininger:
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST,
Journal of Electronic Testing, Theory and Application (JETTA),vol. 20, pp 611-622, 2004.
- V. Saposhnikov, Vl. Saposhnikov M., A. Morozov, M. Gössel:
"Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits;,
10th IEEE International On-Line Testing Symposium, pp. 25-31, Madeira, Portugal, Juli 2004.
- V. Otscheretnij, D. Marienfeld, E. S. Sogomonyan, M. Gössel:
"Self-checking Code-disjoint Carry-select Adder with Low Area Overhead by Use of Add1-Circuits",
10th IEEE International On-Line Testing Symposium, pp. 31-36, Madeira, Portugal, Juli 2004.
- D. Marienfeld, E. S. Sogomonyan, V. Otscheretnij, M. Gössel:
"A New Self-checking Multiplier by Use of a Code-disjoint Sum-bit Duplicated Adder",
9th IEEE European Test Symposium, Digest of Papers, pp. 73-78, Corsica, France, May 2004.
- A. Morozov, M. Gössel, V. V. Saposhnikov, Vl. V. Saposhnikov:
"Complementary Circuits for On-Line Detection for 1-out-of-3 Codes",
ARCS 2004 - Organic and Pervasive Computing, pp. 76-83, Augsburg, 2004.
- E. S. Sogomonyan, D. Marienfeld, V. Otscheretnij, M. Gössel:
"Self-checking Carry-select Adder with Sum-bit Duplication",
ARCS 2004 - Organic and Pervasive Computing, pp. 84-91, Augsburg, 2004.
- A. Leininger, M. Gössel, P. Muhmenthaler:
"Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes",
Design, Automation and Test in Europe Conference - DATE, pp. 1302-1307, IEEE Press, Paris, France, 2004.
- E. S. Sogomonyan, D. Marienfeld, V. Otscheretnij, M. Gössel:
"A New Self-checking Sum-bit Duplicated Carry-select Adder",
Design, Automation and Test in Europe Conference - DATE, pp. 1360-1361, IEEE Press, Paris, France, 2004.
2003
- M. Gössel, A. Morozov, V. V. Saposhnikov, Vl. V. Saposhnikov:
"Logic Complement, a New Method of Checking the Combinational Circuits",
Automation and Remote Control, N.64, Vol.1, pp. 153-161, January, 2003.
- B.B. Bhattacharya, A. Dmitriev and M. Goessel:
"Zero-Aliasing Space Compaction of Test Responses using a Single Periodic Output",
IEEE Transactions on COMPUTERS, pp. 1646-1651, Vol.52, Num.12, ISSN 0018-9340, Dezember, 2003.
- R.Karri, G. Kouznetzov and M.Goessel:
"Parity-Based Concurrent Error Detektion in Symmetric Block-Ciphers",
Proc. ITC 2003, pp. 919-926, Charlotte, NC, USA, 3 Sen. - 2 Okt., 2003.
- A.D. Singh, M. Seuring, M. Goessel and
E. Sogomonyan:
"Multimode Scan: Test per Clock BIST for IP Cores",
ACM Transactionss on Design Automation of Electronic Systems, October 2003, Vol. 8, Num. 4, pp. 491-505.
- R. Karri, G. Kuznetsov and M.Goessel:
"Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers",
in: C.D. Walter, C.K. Koc and Ch. Paar (Eds) "Criptographic Hardware and Embended Systems - CHES 2003"
(5th International Workshop),
(LNCS 2779), Springer-Verlag 2003, pp. 113-124, Cologne, Germany, September 2003.
- F. Börner, A. Bulatov, P. Jeavons, A. Krokhin:
"Quantified Constraints: Algorithms and Complexity",
in: M. Baatz, J.A. Makowsky (Eds.) "Computer Science Logic (17th International Workshop CSL 2003)",
(LNCS 2801), Springer-Verlag 2003, pp. 58-70.
- K. Mohanram, E. S. Sogomonyan, M. Gössel, N. A. Touba:
"Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits",
9th International On-Line Testing Symposium, pp. 35-40, IEEE Press, Kos, Greece, 2003.
- V. Otscheretnij, M. Gössel, E. S. Sogomonyan, D. Marienfeld:
"A Modulop Checked Self-Checking Carry Select Adder",
9th International On-Line Testing Symposium, pp. 25-29, IEEE Press, Kos, Greece, 2003.
- M. Gössel, K. Chakrabarty, V. Otscheretnij, A. Leininger:
"Identification of Failing Vectors using Signature Analysis with Application to Scan-BIST",
6th International Workshop on Design and Diagnostic of Electronic Circuits and Systems, pp. 81-86, IEEE Press,
Poznan, Poland, 2003.
- M. Gössel, A. Leininger, K. Chakrabarty, V. Otscheretnij:
"Signature Analysis for Identifying Failing Vectors",
Tagungsband 15. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen",
pp.51-54, Timmendorfer Strand, 2003.
- Saposhnikov V.Vl., Saposhnikov Vl.Vl., Morozov A.V, Gössel M.:
"Logisches Komplement, eine neue Methode zur Überwachung kombinatorischer Schaltungen" (russ.),
Avtomatika i Telemechanika, 2003, Number.1, pp.169-178.
2002
- Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty:
"Robust Space Compaction of Test Responses",
11th Asian Test Symposium (ATS'02), pp. 254-259, November 18-20, 2002, Hyatt Regency Guam, Guam, USA.
- Saposhnikov V.Vl., Saposhnikov Vl.Vl., Dmitriev A.V, Morozov A., Gössel M.:
"On-line Fehlererkennung kombinatorischer Schaltungen durch komplimentäre Schaltungen. Elektroniesche Modelierung." (russ.),
Avtomatika i Telemechanika, 2002, Vol.24, Number.6, pp.79-94.
- D.Marienfeld, E.S.Sogomonyan, V. Otscheretnij, M.Gössel:
"A New Self-checking Code-disjoint Carry-skip Adder",
8th IEEE IOLTW (On-Line Testing Workshop), pp. 39-43, IEEE Press, Hotel Delos - Isle of Bendor, France,
8-10 July 2002
- F. Börner, R. Pöschel and V. Sushchanski:
"Boolean Systems of Relations and Galois connections.",
Acta Sci. Math. (Szeged) 68 (2002), 535-560.
- D.Marienfeld, V. Otscheretnij, M.Gössel, E.S.Sogomonyan:
"Partially duplicated Code-disjoint Carry-skip Adder",
17th IEEE International Symposium on DEFECT and FAULT TOLERANCE in VLSI Systems, pp. 78-86, IEEE Press,
November 2002
- B.B. Bhattacharya, A. Dmitriev, M. Gössel and K. Chakrabarty:
Synthesis of Single-Output Space Compactor for Scan-Based Sequential Circuits
IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated circuits and systems, October 2002, Vol. 21, Num. 10,
p.p. 1171-1179
- Goessel, M, Sing, A. and E. Sogomonyan:
Scan-Path with Directly Duplicated and Inverted Duplicated Registers.
Proc. 20th VLSI Test Symposium, Monterey, CA, pp. 47-52, 2002
- Saposhnikov, V., Morozov, A., Saposhnikov, Vl. and Gössel, M.:
Concurrent Checking By Use of Complementary Circuits for 1-out-of-3 Codes,
Proc. 5th IEEE Design aund Diagnostics of Electronic Circuit & Systems, 5th DDECS'02 Workshop, pp. 404-407, 2002.
- G. Kusnezov, M.Gössel:
A Code-disjoint Multiplier with Parity encoded Inputs and Outputs checked by a Residue Code,
ARCS-2002, pp. 67-70, Karlsruhe, April 2002
- Liu, Ch., Chakrabarty, K. and Goessel, M.:
An Interval-based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment,
DATE, pp.382-386, 2002.
2001
- E.S.Sogomonyan, V. Otscheretnij, M.Gössel:
A New Code-disjoint Sum-bit Duplicated Carry Look-ahead Adder for Parity Codes,
10th Asian Test Symposium, pp. 365-370, IEEE Press, November 2001
- M.Gössel, V. Otscheretnij, S.Chakrabarty:
Diagnosis by repeated application of specific test inputs and by output monitoring of the MISA,
10th Asian Test Symposium, pp. 57-62, IEEE Press, November 2001
- M. Gössel,A. Dmitriev, V. Saposhnikov, Vl. Saposhnikov:
Untersuchung von Eigenschaften Selbstdualer, Selbstpruefender Sequentieller Schaltungen. (in russ.)
Avtomatika i Telemechanika, No 4, S. 148-159, 2001.
- E.S.Sogomonyan, A.Morosov, M.Gössel, A.Singh and J.Rzeha:
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging.
19th IEEE VLSI Test Symposium, pp. 184-189, IEEE Press, 2001
- A.Morosov, K.Chakrabarty, M.Gössel and B.Bhattacharya:
Design of Parameterizable Error-propagating Space Compactors for Responsae Observation.
19th IEEE VLSI Test Symposium, pp. 48-53, IEEE Press, 2001
- V. Ocheretnij, M.Gössel, E.S.Sogomonyan:
Code-disjoint carry-dependent sum adder with partial look-ahead.
7th IEEE International On-Line Testing Workshop, pp. 147-152, IEEE Press, Juli 2001
- H. Hartje, I. Neumann, D. Stoffel, W. Kunz:
Cycle Time Optimization by Timing Driven Placement with Simultaneous Netlist Transformations
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. V-359 - V-362, Mai 2001, Sydney, Australia
- Börner, F.:
Total multifunctions and relations.
Contributions to General Algebra 13, 2001, pp. 23-35.
- B. B. Bhattacharya, A. Dmitriev, M. Goessel and K. Chakrabarty:
Synthesis of single-output space compactors with application to scan-based IP cores
Proc. Asia South Pacific Design Automation Conference, pp. 496-501, 2001.
2000
- Gössel, M., Morosov, A., Saposhnikov, V., Saposhnikov, V.:
Der Entwurf kombinatorischer selbstprüfender Schaltungen auf der Grundlage von selbstdualen Funktionen. (russ.)
Avtomatika i Telemechanika, No 2, 2000, S. 151-163.
- Morozov, A., Saposhnikov, V., Saposhnikov, Vl. and Gössel, M.:
New Self-checking Circuits by Use of Berger-Codes.
Proc. 6th IEEE On-line Testing Workshop, Palma de Mallorca, pp. 141-146, 2000.
- Gössel, M., Saposhnikov, Vl., Dmitriev, A. and Saposhnikov, V.:
A New Method for Concurrent Checking by Use of a 1-out-of-4 Code.
Proc. 6th IEEE On-line Testing Workshop, Palma de Mallorca, pp. 147-152, 2000.
- D. Das, N. Touba, M. Seuring, and M. Gössel:
Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes.
Proc. 6th IEEE On-line Testing Workshop, Palma de Mallorca, pp. 171-176, 2000.
- Börner, F.:
Krasneralgebren.
Logos Verlag Berlin, 2000.
- Bhattacharya, B.B., Dmitriev, A. and M. Gössel:
Zero-aliasing space compresion using a single periodic output and its application to testing of embedded cores.
Proc. 13th Int. Conf. on VLSI Design, IEEE CS Press, pp. 382-387, 2000.
- A. Dmitriev, V. Saposhnikov, Vl. Saposhnikov, M. Gössel, Vl. Moschanin and A. Morosov:
New Self-dual Circuits for Error Detection and Testing
VLSI Design, Overseas Publishers Association, Vol. 11, pp. 1-21, 2000.
- V. Ocheretnij, Vl. Saposhnikov, V. Saposhnikov, M.Goessel:
A New Method of Redundancy Addition for Circuit Optimization
Proc. 26th Euromicro Conference, IEEE CS Press, Vol. 1, pp. 172-179, 2000
- M. Seuring, K. Chakrabarty:
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions
Proc. 18th IEEE VLSI Test Symposium, Montreal, 213-219, 2000.
1999
- E. Sogomonyan, A.Singh and M. Goessel:
A Multi-Mode Scannable Memory Element for High Test Efficiency and Delay Testing,
Journal of Electronic Testing, Theory and Application (JETTA),vol. 15, pp 87-96 1999.
- I. Neumann, D. Stoffel, H. Hartje, W. Kunz:
Cell Replication and Redundancy Elimination During Placement for Cycle Time Optimization,
ICCAD99, November 1999, San Jose, CA, US
- Gössel,M., Dmitriev, A. Saposhnikov,V, und Saposhnikov, Vl.:
Eine selbsttestende Struktur zur On-line Fehlererkennung in kombinatorischen Schaltungen,
(russ.) Avtomatika i Telemechanika 1999, No 11, S. 162-164.
- Saposhnikov,V., Saposhnikov, Vl. Goessel, M. and Morosov, A.:
A Method of Construction of Combinational Self-checking Units with Detection of all Single Faults,
Engineering Simulations, vol 16, pp. 745-756, 1999
- A. Singh, E. Sogomonyan, M. Gössel, M. Seuring:
Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element,
Proc. International Test Conference 1999, pp. 227-235, September 1999, Atlantic City, NJ, US.
- M. Seuring, M. Gössel:
A structural approach for space compaction for sequential circuits,
Proc. Defect and Fault Tolerance in VLSI Systems 1999, pp. 286-293, November 1999, Albuquerque, NM, US.
- V. Ocheretnij, Vl. Saposhnikov, V. Saposhnikov, M.Goessel:
A New Method of Redundancy Addition for Circuit Optimization
Preprint 008/1999, November 1999, ISSN 0946-7580
- Vl. Saposhnikov, V. Moshanin, V.Saposhnikov and M.Goessel:
Experimental Results for Self-Dual Multi-Output Combinational Circuits
Journal of Electronic Testing, Theory and Application 15, 295-300, 1999.
- A. Dmitriev, V.V. Saposhnikov, Vl.V. Saposhnikov, M. Goessel:
Self-dual Sequential Circuits for Concurrent Checking,
Compendium of Papers/Handout, IEEE European Test Workshop, May 25-28th, 1999 Constance, Germany
- A. Dmitriev, V.V. Saposhnikov, Vl.V. Saposhnikov, M. Goessel:
Concurrent Checking of Sequential Circuits by AlternatingInputs,
Proc. 11. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", pp. 8-11, Germany,
Potsdam-Hermannswerder, February 1999.
- M. Seuring:
Built-In Self Test mit Multi-Mode Scannable Memory Elementen,
Proc. 11. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", pp. 22-25, Germany,
Potsdam-Hermannswerder, February 1999.
- M. Seuring, M. Gössel:
A Structural Method for Output Compaction of Sequential Automata Implemented as Circuits,
Pre-Proc. 4. Workshop on Implementing Automata, pp. XVI 1-6, Germany, Potsdam, July 1999.
- A. Morosov, M. Gössel, H. Hartje:
Reduced Area Overhead of The Input Parity for Code-Disjoint Circuits
5th IEEE International On-Line Testing Workshop, pp. 162-167, IEEE Press, Juli 1999
- Vl. Saposhnikov, V. Ocheretnij, V. Saposhnikov, M. Gössel:
Modified TMR-system with reduced hardware overhead
5th IEEE International On-Line Testing Workshop, pp. 227-230, IEEE Press, Juli 1999
- V. Otscheretnij, Vl. Saposhnikov, V. Saposhnikov, M. Gössel:
Fault-Tolerant Self-dual Circuits
Proc. 11. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", pp. 92-95, Germany,
Potsdam-Hermannswerder, February 1999.
- F. Börner:
A remark on the finite lattice representation problem.
Contributions to General Algebra 11 (1999), pp. 5-38.
- M. Gössel, Sogomonyan, E.S., Morosov, A.:
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces.
Proc. 17th VLSI Test Symposium, pp. 49-56, 1999.
1998
- Börner, F. und Haddad, L.:
Generating sets for clones and partial clones
Proc. 28th ISMVL, pp. 363 - 368, Fuknota, Japan, May 1998.
- Börner, F. und Haddad, L.:
Maximal partial clones with no finite basis
Algebra Universalis 40(1998), pp. 453 - 476.
- Saposhnikov, Vl., Otscheretnij, V., Saposhnikov, V., Gössel, M.:
Design of Fault-Tolerant Circuits by Self-dual Duplication
Proc. 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 129 - 136,
Szczyrk, Poland, 1998.
- Gössel, M., Sogomonyan, E.:
On-Line Test auf der Grundlage eines die Paritï¿œt erhaltenden Signaturanalysators
(russ.) Avtomatika i. Telemechanika, No. 5, pp. 162 - 170,1998.
- Saposhnikov, Vl.V., Saposhnikov, V.V.,Dmitriev, A.,Goessel, M.:
Self-dual duplication for Error Detection
Proc. 7th Asian Test Symposium, pp. 296-300, Singapore, December 1998.
- M. Seuring, M. Goessel, E. Sogomonyan:
Ein strukturelles Verfahren zur Kompaktierung von Schaltungsausgaben für On-line-Fehlererkennung und Selbsttest
Proc. 10. Workshop "Testmethoden und Zuverlï¿œssigkeit von Schaltungen und Systemen", Herrenberg, 1998.
- Bogue, T., Goessel, M., Juergensen, H., Zorian, Y.:
Built-in Self-Test with an Alternating Output
Proc. DATE (Design, Automation and Test in Europe) 1998, pp. 180- 184, Paris, 1998
- Sogomonyan, E.S., Singh, A.D., Goessel, M.:
A Scan Based Concurrent BIST Approach for Low Cost On-Line Testing
Proc. 4th IEEE International On-Line Testing Workshop, pp. 52- 55, Capri, Italy, 1998
- Otscheretnij, V., Goessel, M., Saposhnikov, Vl.V., Saposhnikov, V.V.:
Fault-Tolerant Self-dual Circuits with Error Detection by Parity- and Group Parity Prediction
Proc. 4th IEEE International On-Line Testing Workshop, pp.124-130, Capri, Italy, 1998
- Moshanin, Vl., Otscheretnij, V., Dmitriev, A.:
The Impact of Logic Optimization on Concurrent Error Detection
Proc. 4th IEEE International On-Line Testing Workshop, pp. 81-84, Capri, Italy, 1998
- Morosow, A., Saposhnikov, V.V., Saposhnikov, Vl.V., Goessel, M.:
Self-Checking Circuits with Unidirectionally Independent Outputs
Journal VLSI Design, Vol 5 No 4. pp. 333-345, 1998
- Saposhnikov, V.V., Morosow,A. Saposhnikov,Vl.V. and Goessel,M.:
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Journal of Electronic Testing: Theory and Applications 12, 41-53, 1998
- Sogomonyan, E. S., Singh, A. D. and Goessel, M.:
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Proc. 16th IEEE VLSI Test Symposium, Monterey, 324-331, 1998
- M. Seuring, M. Goessel, E. Sogomanyan:
A Structural Approach for Space Compaction for Concurrent Checking and BIST
Proc. 16th IEEE VLSI Test Symposium, Monterey, 354-361, 1998.
1997
- Stoffel, D., Kunz, W., Gerber, S.:
AND/OR Reasoning Graphs for Determining Prime Implicants in Multi-Level Combinational Networks
Proc. Asia and South Pacific Design Automation Conference, 1997
- Hlawiczka A., Gössel M., Sogomonyan E. S.:
A Linear Code-Preserving Signature Analyzer COPMISR
Proceedings of 15th IEEE VLSI Test Symposium, Computer Society Press, pp.350-355, Monterey, USA, 1997
- Saposhnikov, Va. V., Morosov, A., Saposhnikov, Vl. V., Gössel, M.:
Design of Self-Checking Unidirectional Combinational Circuits with low Area Overhead
Journal of Electronic Testing: Theory and Applications, 1997
- Kunz, W., Stoffel, D., Menon, P.:
Logic Optimization and Equivalence Checking by Implication Analysis
IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol. 16, no. 3, pp. 266-281, March 1997
- Hartje, H., Sogomonyan E. S., Gössel M.:
Code Disjoint Circuits for Parity Codes
Asian Test Symposium, Akita, Japan, November 1997
- Dmitriev A., Saposhnikov Vl. V., Gössel M., Saposhnikov V. V.:
On-Line Testing by Self-Dual Duplication
Tagungsband des 9. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen",
Bremen, pp.43-47, März, 1997
- Morosov A., Saposhnikov V. V., Saposhnikov Vl. V., Gössel M.:
Ein Transformationsalgorithmus einer kombinatorischen Schaltung in eine monotone Schaltung
Tagungsband des 9. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen",
Bremen, pp.78-81, März, 1997
- Saposhnikov Vl. V., Moshanin V., Saposhnikov V. V., Gössel M.:
Self-Dual Multi-Output Combinational Circuits with Output Data Compaction
Compendium of Papers IEEE European Test Workshop, Cagliari, Italy, 1997
- Hartje H., Gössel M., Sogomonyan E. S.:
Synthesis of Code-Disjoint Combinational Circuits
Compendium of Papers IEEE European Test Workshop, Cagliari, Italy, 1997
- Gössel M., Sogomonyan E. S.:
New Totally Self-Checking Ripple and Carry Look-Ahead Adders
3rd IEEE International On-Line Testing Workshop, pp.36-40, Crete, Greece, July 1997
- Dmitriev A., Saposhnikov Vl. V., Gössel M., Saposhnikov V. V.:
Self-Dual Duplication - a New Method for On-Line Testing
3rd IEEE International On-Line Testing Workshop, pp.213-217, Crete, Greece, July 1997
- Morosov A., Saposhnikov Vl. V., Saposhnikov V. V., Gössel M.,:
Design of Self-Dual Fault-Secure Combinational Circuits,
3rd IEEE International On-Line Testing Workshop, pp.233-237, Crete, Greece, July 1997
- Wildner U.:
Experimental Evaluation of Assigned Signature Checking With Return Address Hashing on Different Platforms
Preprints of Sixth International Working Conference on Depenable Computing for Critical Applications,
pp. 1-17, Grainau, Germany, 1997
- Stoffel D., Kunz W.:
Record & Play: A Structural Fixed Point Iteration for Sequential Circuit Verification
Proc. of the ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD), November 1997
1996
- Gössel, M., Sogomonyan, E. S.:
A Parity-Preserving Multi-Input Signature Analyzer and its Application for Concurrent Checking and BIST
Journal of Electronic Testing: Theory and Applications, Vol. 8, pp. 165 - 177, 1996
- Gössel, M., Sogomonyan, E. S.:
A New Self-Testing Parity Checker for Ultra-Reliable Applications
Computer Aided Design, Test and Evaluation for Dependability (Ed. Y. Min and D. Tang), International Academic Publishers,
pp. 246 - 251, Peking, 1996
- Kundu, S., Sogomonyan, E. S., Gössel, M., Tarnick, S.:
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers, Vol. 45, No 3, pp. 379 - 380, 1996
- Kunz, W., Reddy, Subodh M., Pradhan, D. K.:
Efficient Logic Verification in a Synthesis Enviroment
IEEE Transactions on Computer-Aided Design, pp. 20 - 32, Januar 199
- Moschanin, W., Saposhnikov, Vl., Saposhnikov, Va., Gössel, M.:
Synthesis of Self-Dual Multi-Output Combinational Circuits for On-line Testing
Proc. 2nd IEEE Int. On-line Testing Workshop, pp. 107 - 111, Biarritz, 1996
- Saposhnikov, Vl. V., Dmitriev, A., Gössel, M., Saposhnikov, Va. V.:
Self-dual parity checking - a new method for on-line testing
Proc. 14th IEEE VLSI Test Symposium, Princeton, New Jersey, USA, pp. 162-168, May 1996
- Sogomonyan, E. S., Gössel, M.:
Concurrently Self-Testing Embedded Checkers for Ultra-Reliable Fault-Tolerant Systems
Proc. 14th IEEE VLSI Test Symposium, Princeton, New Jersey, USA, pp. 138-144, May 1996
- Stoffel, D., Kunz, W.:
Logic Equivalence Checking by Optimization Techniques
Computer Aided Design, Test and Evaluation for Dependability (Ed. Y. Min and D. Tang), International Academic Publishers,
pp. 85 - 90, Peking, 1996
- Saposhnikov, Va. V., Morosov, A., Saposhnikov, Vl. V., Gössel, M.:
Design of Self-Checking Unidirectional Combinational Circuits with low Area Overhead
Proc. 2nd IEEE Int. On-line Testing Workshop, pp. 56 - 67, Biarritz, 1996
- Wildner, U.:
Compiler Assisted Self-Checking of Structural Integrity Using Return Address Hashing
Proc. EDCC-2, pp. 161 - 177, Springer-Verlag LNCS 1150, Taormina, Italien, Oktober 1996
- Pradhan, D., Chatterjee, M., Swarna, M., Kunz, W.:
Implication-Based Gate-Level Synthesis for Low-Power
Proc. IEEE Symposium of Low Power Electronics and Design, 1996
1995
- Chatterjee, M., Pradhan, D., Kunz, W.:
ATPG-based Transformations for Random-Pattern Testable Logic Synthesis
Proc. 1995 ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD), November 1995
- Gohlke, M.:
A New Approach for Model-Based Recognition Using Colour Regions
DICTA 95 (Digital Image Computing Techniques and Applications),
University of Queensland, Brisbane, Australien, pp. 528 - 533, Dezember 1995
- Sogomonyan, E. S., Gössel, M.:
A New Parity Preserving Multi-Input Signature Analyser
Proc. 1st IEEE International On-line Testing Workshop, Nice, France, pp. 211 - 215, 1995
- Tarnick, S.:
Controllable Self-Checking Checkers for Conditional Concurrent Checking
IEEE Transactions on Computer-Aided Design, Vol. 14, No. 5, May 1995, pp. 547-553.
- S.M. Reddy, W. Kunz, and D.K. Pradhan:
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment
Proc. ACM/IEEE Design Automation Conference, San Francisco, CA, June 1995, pp. 414-419
- Bogue, T., Jürgensen, H., and Gössel, M.:
BIST with Negligible Aliasing through Random Cover Circuits
Proc. Asia South Pacific Design Automation Conference, Chiba, Japan, August/September 1995
- Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., Courtois, B.:
Built-In Test for Circuits with Scan Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers
IEEE Transactions on Computers, Vol. 44, No. 2, pp. 223 - 233, Februar 1995
1994
- Böhlau, P.:
Zero Aliasing Compression Based on Groups of Weakly Independent Outputs in Circuits with High Complexity for Two Fault
Models
Proc. First European Dependable Computing Conference, EDCC-1, Berlin, Germany, 1994, Lecture Notes in Computer Science 852,
Springer-Verlag, Berlin, pp. 289-306
- Bogue, T., Jürgensen, H., and Gössel, M.:
Design of Cover Circuits for Monitoring the Output of a MISR
Proc. IEEE Int. Workshop on Defect and Fault Tolrance in VLSI Systems, Montreal, 1994, pp. 124-132
- Cobernuss, M.:
Bused Interconnection Network for Parallel Memory with Linear Storage
Proc. Parcella 94, Potsdam, Germany, 1994, pp. 169-178
- Gerber, S. and Gössel, M.:
Detection of Permanent Faults of a Floating Point Adder by Pseudoduplication
Proc. First European Dependable Computing Conference, EDCC-1, Berlin, Germany, 1994, Lecture Notes in Computer Science 852,
Springer-Verlag, Berlin, pp. 327-335
- M. Gössel, A.A. Morosov, V.V. Saposhnikov, and Vl.V. Saposhnikov:
Design of Combinational Self-Testing Devices with Unidirectionally Independent Outputs (in russian)
Avtomatika i Telemechanika, no. 7, 1994, pp. 148-160
- M. Gössel and E.S. Sogomonyan:
Code Disjoint Self-Parity Combinational Circuits for Self-Testing, Concurrent Fault Detection and Parity Scan Design
Proc. 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, April 1994, pp. 151-157
- M. Gössel and E.S. Sogomonyan:
Self-Parity Combinational Circuits for Self-Testing, Concurrent Fault Detection and Parity Scan Design
IFIP Transactions A-42, Computer Science and Technology, VLSI-93, North-Holland, 1994, pp. 103-111
- W. Kunz and P. Menon:
Multi-Level Logic Optimization by Implication Analysis
Proc. ACM/IEEE Int. Conference on Computer-Aided Design (ICCAD-94), San Jose, CA, November 1994, pp. 6-13
- W. Kunz and D.K. Pradhan:
Recursive Learning: A New Implication Technique for Efficient Solutions to CAD Problems: Test,
Verification and Optimization
IEEE Transactions on Computer-Aided Design, Vol. 13, No. 9, September 1994, pp. 1143-1158
- W. Kunz:
Ein effizientes Verfahren fuer die Logikverifikation
GI/GME/ITG-Fachtagung "Rechnergestuetzter Entwurf und Architektur mikroelektronischer
Systeme", Oberwiesental, Germany, May 1994, pp. 52-61
- W. Kunz:
Ein neuer Ansatz fuer die Optimierung mehrstufiger logischer Schaltungen
GI/GME/ITG-Fachtagung "Rechnergestuetzter Entwurf und Architektur mikroelektronischer
Systeme", Oberwiesental, Germany, May 1994, pp. 52-61
- S. Tarnick:
Controllable Self-Checking Checkers for Conditional Concurrent Checking
Proc. 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, April 1994, pp. 144-150
- S. Tarnick:
Bounding Error Masking in Linear Output Space Compression Schemes
Proc. 3rd Asian Test Symposium, Nara, Japan, November 1994, pp. 27-32
1993
- Böhlau, P.:
Design of Self-Checking Circuits for Unsystematic Codes
Proc. 36th Midwest Symposium on Circuits and Systems, Detroit, MI, August 1993, pp. 542-545
- Gössel, M., Jürgensen, H.:
Monitoring BIST by Covers
Proc. EURODAC 93, Hamburg, Germany, 1993, pp. 208-213
- W. Kunz and D.K. Pradhan:
Accelerated Dynamic Learning for Test Pattern Generation in Combinational Circuits
IEEE Transactions on Computer-Aided Design, Vol.12, No. 5, May 1993, pp. 684-694
- Kunz, W.:
HANNIBAL: An Efficient Tool for Logic Verification Based on Recursive Learning
Proc. IEEE/ACM Int. Conference on Computer-Aided Design (ICCAD-93), Santa Clara, CA, November 1993, pp. 538-543
- E.S. Sogomonyan and M. Gössel:
Design of Self-Parity Combinational Circuits for Self-Testing and On-Line Fault Detection
Proc. Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Venice, Italy, 1993, pp. 239-245
- E.S. Sogomonyan and M. Gössel:
Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs
Journal of Electronic Testing (JETTA), Vol. 4, 1993, pp. 267-281
- S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick:
An Efficient BIST Scheme Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
Proc. IEEE/ACM Int. Conference on Computer-Aided Design (ICCAD-93), Santa Clara, CA, November 1993,
pp. 572-577